AM3358: Could give us a reference design to satisfaction below request

Gabriel Wang1

Part Number: AM3358
Other Parts Discussed in Thread: SYSCONFIG

Hi Expert

We have some problems in designing our products and would like to help.Could give us a reference design to satisfaction below request ?

Background: Our machine is based on the DESIGN of AM3358(324PIN), because we need to start the machine faster, so we choose the NorFlash chip design.

Prerequisites:

1. DDR3L (MT41K256M16HA-125)

2. RMII1(100m Network)

3. LCD(RGB-480*800)

4. NorFlash (MT28EW256ABA),256Mbit

5. NandFlash(MT29F8G08ABAB), 8Gbit (or larger)

6. The TF card

I refer to TRM manual 7.1.2

I have carried out pin configuration in TI PinMux Tool and found that the conditions cannot be met. It may be that some parts are not properly configured. I hope to obtain your technical support.

My configuration is as follows:

1. DDR3L

2. RMII1(100m Network)

3. LCD(RGB-480*800)

NorFlash(MT28EW256ABA)256Mbit, address line has 24, data line has 16 and control line, considering the sharing of data line + asynchronous or synchronous mode are not able to go on, occupy the LCD pin, do not know how to deal with, hope to get a help.

I have seen the design of tmdxice3359_sch_3h0013_v2_1a about NOR Flash (16 Mbit) on the official website, but it cannot meet the design of 256Mbit. Can you provide a reference design for designing NAND Flash&NOR Flash together? (or help to configure TI PinMux Tool, provide a reference).

Consultation the second option:

A. DDR3L (MT41K256M16HA-125)

B. RMII1(100 MBIT Network)

C. LCD(RGB-480*800)

D. NorFlash (MT28EW256ABA),256Mbit

E. eMMC (MTFC8GAMALBH), 8 gb

I noted in the TRM manual that MMC1 has a chance to be larger than 4Gb; The MMC0 limit is 4Gb.

Is it feasible? Reserve MMC1 channels for eMMC. Is there a reference design for that? (or provide a TI PinMux Tool configuration file)

over 3 years ago

0 Kallikuppa Sreenivasa over 3 years ago

TI__Guru**** 192189 points

Hello Gabriel Wang1,

Thank you for the query.

Let me review the requirements.

Checking if you Have started the design or still doing feasibility study ?

Regards,

Sreenivasa

0 Gabriel Wang1 over 3 years ago in reply to Kallikuppa Sreenivasa

Genius 4725 points

Hi Kallikuppa

We had started the design and now we need draw the schmetic as soon as possible .

0 Kallikuppa Sreenivasa over 3 years ago in reply to Gabriel Wang1

TI__Guru**** 192189 points

Hello Gabriel Wang1,

Thank you for the note.

I am reviewing the inputs . Please expect delay in response duet US holiday.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 192189 points

Hello Gabriel Wang1,

Could you please share the pin configuration that you have worked for both the designs.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 192189 points

Hello Gabriel Wang1,

Could you please share the pinmux configuration that you have worked for both the designs for us to verify.

Regards,

Sreenivasa

0 Gabriel Wang1 over 3 years ago in reply to Kallikuppa Sreenivasa

Genius 4725 points

Dear Sreenivasa

This ZIP is configuartion

0 Kallikuppa Sreenivasa over 3 years ago in reply to Gabriel Wang1

TI__Guru**** 192189 points

Hello Gabriel Wang1,

Thank you for the inputs.

I will review and inputs an update you.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 192189 points

Hello Gabriel Wang1,

Thank you for the inputs.

I will review the inputs and update you.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 192189 points

Hello Gabriel Wang1,

Let me check internally and comeback to you regarding the MMC memory size.

I noted in the TRM manual that MMC1 has a chance to be larger than 4Gb; The MMC0 limit is 4Gb.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 192189 points

Hello Gabriel Wang1,

Can you please use the below link to generate the sysconfig file and share.

https://dev.ti.com/sysconfig/#/start

For the listed options looks like using the 24 bit LCD is a major cause of conflict in addition to other issues including 2 MMC interfaces.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 192189 points

Hello Gabriel Wang1,

The below link could help in case you are looing to use MMC for boot.

(+) AM3358: SD card boot from MMC1 - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

0 Gabriel Wang1 over 3 years ago in reply to Kallikuppa Sreenivasa

Genius 4725 points

Dear Sreenivsa

We need NandFlash(8Gb)+NorFlash (64MB)+ DDR3L solution, but must keep the LCD interface and RMII1. I have made it clear that MMC0 is not allowed to connect more than 4Gb. GPMC interfaces can share NOR+NAND, but we won't set it.

Below is the configure file ,thanks!

Fullscreen 6052.am335x_pinmux_data.c Download

/**
 * Note: This file was auto-generated by TI PinMux on 2022/5/31 at 上午11:51:30.
 *
 * \file  am335x_pinmux_data.c
 *
 * \brief  This file contains the pin mux configurations for the boards.
 *         These are prepared based on how the peripherals are extended on
 *         the boards.
 *
 * \copyright Copyright (CU) 2022 Texas Instruments Incorporated -
 *             http://www.ti.com/
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include "types.h"
#include "pinmux.h"
#include "am335x_pinmux.h"

/** Peripheral Pin Configurations */

#ifndef BUILDCFG_MOD_GPMC
#define BUILDCFG_MOD_GPMC
#endif /* BUILDCFG_MOD_GPMC */

#ifndef BUILDCFG_MOD_LCDC
#define BUILDCFG_MOD_LCDC
#endif /* BUILDCFG_MOD_LCDC */

#ifndef BUILDCFG_MOD_CPSW
#define BUILDCFG_MOD_CPSW
#endif /* BUILDCFG_MOD_CPSW */


#if defined(BUILDCFG_MOD_GPMC)

static pinmuxPerCfg_t gGpmc0PinCfg[] =
{
    {
       /* My-Nor-NandFlash -> gpmc_a1 -> V14 */
       PIN_GPMC_A1, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_a2 -> U14 */
       PIN_GPMC_A2, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_a3 -> T14 */
       PIN_GPMC_A3, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_a6 -> U15 */
       PIN_GPMC_A6, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_a7 -> T15 */
       PIN_GPMC_A7, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_a8 -> V16 */
       PIN_GPMC_A8, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_a9 -> U16 */
       PIN_GPMC_A9, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_ad7 -> T9 */
       PIN_GPMC_AD7, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_ad6 -> R9 */
       PIN_GPMC_AD6, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_ad5 -> V8 */
       PIN_GPMC_AD5, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_ad4 -> U8 */
       PIN_GPMC_AD4, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_ad3 -> T8 */
       PIN_GPMC_AD3, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_ad2 -> R8 */
       PIN_GPMC_AD2, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_ad1 -> V7 */
       PIN_GPMC_AD1, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_ad0 -> U7 */
       PIN_GPMC_AD0, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_wait0 -> T17 */
       PIN_GPMC_WAIT0, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_wait1 -> V12 */
       PIN_GPMC_CLK, 0, \
       ( \
           PIN_MODE(2) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_be1n -> U18 */
       PIN_GPMC_BE1N, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_advn_ale -> R7 */
       PIN_GPMC_ADVN_ALE, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_oen_ren -> T7 */
       PIN_GPMC_OEN_REN, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_wen -> U6 */
       PIN_GPMC_WEN, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_be0n_cle -> T6 */
       PIN_GPMC_BE0N_CLE, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-Nor-NandFlash -> gpmc_csn0 -> V6 */
       PIN_GPMC_CSN0, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {PINMUX_INVALID_PIN}
};

static pinmuxModuleCfg_t gGpmcPinCfg[] =
{
    {0, TRUE, gGpmc0PinCfg},
    {CHIPDB_INVALID_INSTANCE_NUM}
};

#endif /* if defined(BUILDCFG_MOD_GPMC) */

#if defined(BUILDCFG_MOD_LCDC)

static pinmuxPerCfg_t gLcdc0PinCfg[] =
{
    {
       /* My-LCD -> lcd_vsync -> U5 */
       PIN_LCD_VSYNC, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_hsync -> R5 */
       PIN_LCD_HSYNC, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_pclk -> V5 */
       PIN_LCD_PCLK, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_ac_bias_en -> R6 */
       PIN_LCD_AC_BIAS_EN, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_memory_clk -> J17 */
       PIN_GMII1_RXDV, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data0 -> R1 */
       PIN_LCD_DATA0, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data1 -> R2 */
       PIN_LCD_DATA1, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data2 -> R3 */
       PIN_LCD_DATA2, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data3 -> R4 */
       PIN_LCD_DATA3, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data4 -> T1 */
       PIN_LCD_DATA4, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data5 -> T2 */
       PIN_LCD_DATA5, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data6 -> T3 */
       PIN_LCD_DATA6, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data7 -> T4 */
       PIN_LCD_DATA7, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data8 -> U1 */
       PIN_LCD_DATA8, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data9 -> U2 */
       PIN_LCD_DATA9, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data10 -> U3 */
       PIN_LCD_DATA10, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data11 -> U4 */
       PIN_LCD_DATA11, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data12 -> V2 */
       PIN_LCD_DATA12, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data13 -> V3 */
       PIN_LCD_DATA13, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data14 -> V4 */
       PIN_LCD_DATA14, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data15 -> T5 */
       PIN_LCD_DATA15, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data16 -> U13 */
       PIN_GPMC_AD15, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data17 -> V13 */
       PIN_GPMC_AD14, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data18 -> R12 */
       PIN_GPMC_AD13, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data19 -> T12 */
       PIN_GPMC_AD12, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data20 -> U12 */
       PIN_GPMC_AD11, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data21 -> T11 */
       PIN_GPMC_AD10, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data22 -> T10 */
       PIN_GPMC_AD9, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-LCD -> lcd_data23 -> U10 */
       PIN_GPMC_AD8, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {PINMUX_INVALID_PIN}
};

static pinmuxModuleCfg_t gLcdcPinCfg[] =
{
    {0, TRUE, gLcdc0PinCfg},
    {CHIPDB_INVALID_INSTANCE_NUM}
};

#endif /* if defined(BUILDCFG_MOD_LCDC) */

#if defined(BUILDCFG_MOD_CPSW)

static pinmuxPerCfg_t gCpsw0PinCfg[] =
{
    {
       /* My-RMII1 -> rmii1_crs_dv -> H17 */
       PIN_GMII1_CRS, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-RMII1 -> rmii1_rxer -> J15 */
       PIN_GMII1_RXER, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-RMII1 -> rmii1_txen -> J16 */
       PIN_GMII1_TXEN, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-RMII1 -> rmii1_txd0 -> K17 */
       PIN_GMII1_TXD0, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-RMII1 -> rmii1_txd1 -> K16 */
       PIN_GMII1_TXD1, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* My-RMII1 -> rmii1_rxd0 -> M16 */
       PIN_GMII1_RXD0, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-RMII1 -> rmii1_rxd1 -> L15 */
       PIN_GMII1_RXD1, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* My-RMII1 -> rmii1_refclk -> H18 */
       PIN_RMII1_REFCLK, 0, \
       ( \
           PIN_MODE(0) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* MyRMII2 -> rmii2_crs_dv -> T13 */
       PIN_GPMC_CSN3, 0, \
       ( \
           PIN_MODE(2) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* MyRMII2 -> rmii2_rxer -> U17 */
       PIN_GPMC_WPN, 0, \
       ( \
           PIN_MODE(3) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* MyRMII2 -> rmii2_txen -> R13 */
       PIN_GPMC_A0, 0, \
       ( \
           PIN_MODE(3) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* MyRMII2 -> rmii2_txd0 -> V15 */
       PIN_GPMC_A5, 0, \
       ( \
           PIN_MODE(3) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* MyRMII2 -> rmii2_txd1 -> R14 */
       PIN_GPMC_A4, 0, \
       ( \
           PIN_MODE(3) | \
           ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)) \
       ) \
    },
    {
       /* MyRMII2 -> rmii2_rxd0 -> V17 */
       PIN_GPMC_A11, 0, \
       ( \
           PIN_MODE(3) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* MyRMII2 -> rmii2_rxd1 -> T16 */
       PIN_GPMC_A10, 0, \
       ( \
           PIN_MODE(3) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {
       /* MyRMII2 -> rmii2_refclk -> H16 */
       PIN_GMII1_COL, 0, \
       ( \
           PIN_MODE(1) | \
           ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)) \
       ) \
    },
    {PINMUX_INVALID_PIN}
};

static pinmuxModuleCfg_t gCpswPinCfg[] =
{
    {0, TRUE, gCpsw0PinCfg},
    {CHIPDB_INVALID_INSTANCE_NUM}
};

#endif /* if defined(BUILDCFG_MOD_CPSW) */


pinmuxBoardCfg_t gAM335xPinmuxData[] =
{
#if defined(BUILDCFG_MOD_GPMC)
    {CHIPDB_MOD_ID_GPMC, gGpmcPinCfg},
#endif /* if defined(BUILDCFG_MOD_GPMC) */
#if defined(BUILDCFG_MOD_LCDC)
    {CHIPDB_MOD_ID_LCDC, gLcdcPinCfg},
#endif /* if defined(BUILDCFG_MOD_LCDC) */
#if defined(BUILDCFG_MOD_CPSW)
    {CHIPDB_MOD_ID_CPSW, gCpswPinCfg},
#endif /* if defined(BUILDCFG_MOD_CPSW) */
    {CHIPDB_MOD_ID_INVALID}
};

5226.am335x_pinmux.h

8662.PinmuxConfigSummary.csv