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AM6442: Data Fault event in SBL on memory read

MH
Intellectual 290 points
Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

Hello,

I'm getting a HwiP_data_abort_handler interrupt triggered when trying to read a byte @ 0x51000000 (GPMC0_DATA). The configuration is described below:

- Using the SBL boot for R5F0_0, MPU zone defined for GPMC0_DATA (0x50000000 with 128MB size, Supervisor RD+WR, User RD+WR and cached).

- After Bootloader_socWaitForFWBoot(), the following is done:

  + GPMC: powered up, clock enabled, reset done (and wait for reset done), parent clock and clock set

  + Confirmed the above all good, read back clock, read REVID ok (GPMC0_CFG).

- When trying to read a byte in GPMC0_DATA memory zone (ldrb r0,[r0] with r0=0x51000000), the HwiP_data_abort_handler() is triggered

the following CP15 registers could point to the problem (DATA_FAULT_ADDRESS = 0x51000000 & DATA_FAULT_STATUS 0x00001008):

CP15_ID_CODE 0x411FC153 Core
CP15_MAIN_ID 0x411FC153 Core
CP15_CACHE_TYPE 0x8003C003 Core
CP15_TCM_TYPE 0x00010001 Core
CP15_MPU_TYPE 0x00001000 Core
CP15_MULTIPROCESSOR_ID 0xC0000000 Core
CP15_PROCESSOR_FEATURE_0 0x00000131 Core
CP15_PROCESSOR_FEATURE_1 0x00000001 Core
CP15_DEBUG_FEATURE_0 0x00010400 Core
CP15_AUXILIARY_FEATURE_0 0x00000000 Core
CP15_MEMORY_MODEL_FEATURE_0 0x00210030 Core
CP15_MEMORY_MODEL_FEATURE_1 0x00000000 Core
CP15_MEMORY_MODEL_FEATURE_2 0x01200000 Core
CP15_MEMORY_MODEL_FEATURE_3 0x00000211 Core
CP15_INSTRUCTION_SET_ATTRIBUTE_0 0x02101111 Core
CP15_INSTRUCTION_SET_ATTRIBUTE_1 0x13112111 Core
CP15_INSTRUCTION_SET_ATTRIBUTE_2 0x21232141 Core
CP15_INSTRUCTION_SET_ATTRIBUTE_3 0x01112131 Core
CP15_INSTRUCTION_SET_ATTRIBUTE_4 0x00010142 Core
CP15_INSTRUCTION_SET_ATTRIBUTE_5 0x00000000 Core
CP15_CURRENT_CACHE_SIZE_ID 0xF01FE019 Core
CP15_CURRENT_CACHE_LEVEL_ID 0x09200003 Core
CP15_CACHE_SIZE_SELECTION 0x00000001 Core
CP15_SYSTEM_CONTROL 0x01E5187D Core
CP15_AUXILIARY_CONTROL 0x0E000020 Core
CP15_COPROCESSOR_ACCESS 0xC0F00000 Core
CP15_DATA_FAULT_STATUS 0x00001008 Core
CP15_INSTRUCTION_FAULT_STATUS 0x00000000 Core
CP15_AUX_DATA_FAULT_STATUS 0x00000000 Core
CP15_AUX_INSTRUCTION_FAULT_STATUS 0x00000000 Core
CP15_DATA_FAULT_ADDRESS 0x51000000 Core
CP15_INSTRUCTION_FAULT_ADDRESS 0x00000000 Core
CP15_MPU_REGION_BASE_ADDRESS 0x50000000 Core
CP15_MPU_REGION_SIZE_ENABLE 0x00000035 Core
CP15_MPU_REGION_ACCESS 0x0000130B Core
CP15_MPU_REGION_NUMBER 0x00000006 Core

Please let me know if you have some thoughts on what could be the cause and how to fix it.

Thank you,

Mehdi

  • 0
    TI__Genius 12330 points

    Dear Mehdi,

    we will look at your query please allow us few days to recreate the issue at our end, or if you could share the sample code creating the issue it will help.

    Regards

    Anshu

  • 0 in reply to Anshu Choudhary
    Intellectual 290 points

    Hi Anshu,

    I'm not sure if the GPMC configuration can affect this data access fault on the GPMC_DATA area, and to make sure you have all the details, here's the full configuration of the GPMC:

    Offset Acronym GPMC0_CFG Physical Address register content
    0h GPMC_REVISION 3B00 0000h 0x00000060
    10h GPMC_SYSCONFIG 3B00 0010h 0x00000000
    14h GPMC_SYSSTATUS 3B00 0014h 0x00000001
    18h GPMC_IRQSTATUS 3B00 0018h 0x00000000
    1Ch GPMC_IRQENABLE 3B00 001Ch 0x00000000
    40h GPMC_TIMEOUT_CONTROL 3B00 0040h 0x00001FF0
    44h GPMC_ERR_ADDRESS 3B00 0044h 0x00000000
    48h GPMC_ERR_TYPE 3B00 0048h 0x00000000
    50h GPMC_CONFIG 3B00 0050h 0x00000A10
    54h GPMC_STATUS 3B00 0054h 0x00000301
    60h + formula GPMC_CONFIG1_i 3B00 0060h + formula 0x00000800
    64h + formula GPMC_CONFIG2_i 3B00 0064h + formula 0x00060600
    68h + formula GPMC_CONFIG3_i 3B00 0068h + formula 0x00040400
    6Ch + formula GPMC_CONFIG4_i 3B00 006Ch + formula 0x03000401
    70h + formula GPMC_CONFIG5_i 3B00 0070h + formula 0x00000606
    74h + formula GPMC_CONFIG6_i 3B00 0074h + formula 0x86000000
    78h + formula GPMC_CONFIG7_i 3B00 0078h + formula 0x00000F51
    7Ch + formula GPMC_NAND_COMMAND_i 3B00 007Ch + formula  
    80h + formula GPMC_NAND_ADDRESS_i 3B00 0080h + formula  
    84h + formula GPMC_NAND_DATA_i 3B00 0084h + formula  
    1E0h GPMC_PREFETCH_CONFIG1 3B00 01E0h 0x00004000
    1E4h GPMC_PREFETCH_CONFIG2 3B00 01E4h 0x00000000
    1ECh GPMC_PREFETCH_CONTROL 3B00 01ECh 0x00000000
    1F0h GPMC_PREFETCH_STATUS 3B00 01F0h 0x00000000
    1F4h GPMC_ECC_CONFIG 3B00 01F4h 0x00001030
    1F8h GPMC_ECC_CONTROL 3B00 01F8h 0x00000000
    1FCh GPMC_ECC_SIZE_CONFIG 3B00 01FCh 0xFFFFF000

    The attached NAND device is on CS0.

    Since GPMC_CONFIG7_0 was set 0xF51, I also tested with MPU zone defined for GPMC0_DATA (0x51000000 with 16MB size, Supervisor RD+WR, User RD+WR and cached), the results were the same: Data Abort when trying to read the results of the NAND ID read from 0x51000000.

    Could it be that the DSMC is blocking this access from R5F0_0 to GPMC0_DATA? (I also tried calling Bootloader_socOpenFirewalls() right after Bootloader_socWaitForFWBoot() but the abort persists).

    Regards,

    Mehdi

  • 0 in reply to MH
    TI__Genius 12330 points

    Thanks Mehdi, for the GPMC Configuration, we are trying to recreate your issue.

    please expect answer by mid of next week

    regards

    Anshu

  • 0 in reply to MH
    Intellectual 290 points

    Hi Anshu,

    Any news on this problem? were you able to reproduce?

    Thank you

  • 0 in reply to MH
    TI__Guru 70871 points

    Hi Mehdi,

     

    Since GPMC_CONFIG7_0 is set to 0xF51, I understand the following:

    • The base address for the CS0 memory region is 0b010001.
    • The CS0 memory region size is 16MB.

    Since the base address is 0b010001 which corresponds to address lines A29-A24, trying to access the memory location 0x51000000 should not be an issue and thus should not raise an error.

    Thus, can you please try out the following:

    • Try increasing the CS0 memory region size via the MASK ADDRESS bitfields. For example, if the size is to be increased to 32MB, GPMC_CONFIG7_0 should be set to 0x751.
    • Check the GPMC configuration once to see if GPMC is correctly configured to interact with the NAND memory device.

     

    Also, if you could share the data sheet of your NAND memory, it may help us better in understanding the issue.

  • 0 in reply to Prashant Shivhare
    Intellectual 290 points

    Hello,

    The problem was traced back to GPMC_CONFIG5.RDACCESSTIME being set to 0 was generating the fault.

    Thank you for your help,

    Mehdi

  • 0 in reply to MH
    TI__Genius 12330 points

    Thanks Mehdi for pointing out an answer