C6678L EVMs PCIe Clock from CDCE62005

Hi Nori,

For the first question, the PCIESSEN switch (SW9) will disable the power and clock domain within the device itself. It has nothing to do with the outside clock generator on the board (CDCE62005). So there are still 100MHz output from CDCE62005.

For the second question, we have tested two devices (C66x VDB to C66x VDB) communication via PCIe link and use its own PCIe clock on each board. It is working in that way as long as the two clocks are clean and accurate. I think the 6678L EVM has the similar clock generator as VDB, so it should be OK to communicate in asynchronous mode on its own clock.

Sincerely,

Steven

Let me add some additional information.  The PCIESSEN bootmode input to the DSP is the only thing controlled by SW9.  The FPGA will drive the level defined by the switch at boot time to the TIMI0 input.  After the boot is complete the FPGA will drive a 24MHz clock into TIMI0.

The PCIE interface has been tested using an AMC-to-SMA breakout board to connect two EVMs together with SMA cables.  In this mode each EVM is using the on-board CDCE62005 to source the PCIE_CLK input.