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SDRAM with C6418

Chris Fiege
Prodigy 30 points

Hey!

 

We are developing a board using the C6418. At the moment we are trying go get the SDRAM to work.

We are using a Micron MT48LC4M32B2-6 128Mbit SDRAM-Chip mapped into CE0 of EMIFA. The EMIFA is clocked at CPU/6. For testing our CPU runs at 300MHz or less. So the SDRAM runs at 50MHz or less.

ECLKOUT1 is enabled in GBLCTL. And ECLKOUT1 runs.... ;)
CE0 is configured to memory-type SDRAM32.
In SDCTL bit RFEN is set. So SDRAM refresh should be enabled.
In SDCTL bit SLFRFR is unset. So SDRAM self-refresh is disabled.
The Layout and timing of the SDRAM *should* be set correctly.
The SDTIM register is set do to four Auto Refreshes every 15,6µs.

Now we are expiring two problems:

First:
We are configuring our EMIFA to do four Auto Refreshes on the SDRAM contents every 15,6µs. If the CPU is idle, we expect the EMIF to produce four Chip-Selects to the SDRAM every 15,6µs. But: There are no access to the SDRAM! Do we need to access the SDRAM first before the EMIF starts to Refresh SDRAM contents?

Next:
If we write a Word into the first Adress of the SDRAM (lets say this is address 0x000) this Word appers at Address 0x000 and 0x100. If we write an other Word 0x101 this Word appers at adress 0x001. The address 0x101is still in the same page (or row) of the SDRAM. And: We can only measure one access to the SDRAM. Is this a known Problem? Or can someone figure out what causes this fault?

 

Thanks :)

 

Regards,
Chris

  • 0
    TI__Guru* 84110 points

    If you have not already done so, please refer to the App Note "TMS320C6000 EMIF-to-External SDRAM Interface" that is available from the C6418 Product Folder on www.ti.com.

    Chris Fiege said:

    We are configuring our EMIFA to do four Auto Refreshes on the SDRAM contents every 15,6µs. If the CPU is idle, we expect the EMIF to produce four Chip-Selects to the SDRAM every 15,6µs. But: There are no access to the SDRAM! Do we need to access the SDRAM first before the EMIF starts to Refresh SDRAM contents?

    4 refreshes in 15us does not seem often enough, so maybe you will get some clarification from the app note and/or the EMIF User's Guide. But the fact that you get no access to the SDRAM's CS0 means that something is mis-configured in your EMIF register settings. Please compare your settings to those in any sample code for the EVM and the GEL file for the EVM. Be sure that all configuration steps are followed, not just the ones for the EMIF.

    Chris Fiege said:

    If we write a Word into the first Address of the SDRAM (lets say this is address 0x000) this Word appears at Address 0x000 and 0x100. If we write an other Word 0x101 this Word appears at address 0x001. The address 0x101 is still in the same page (or row) of the SDRAM. And: We can only measure one access to the SDRAM. Is this a known Problem? Or can someone figure out what causes this fault?

    This sounds like a hardware issue. Look for a stuck or open address line going to the SDRAM.