AM6442: UDMA failed to trigger interruptions

Katherine Wang

Part Number: AM6442
Other Parts Discussed in Thread: DP83869

Hi Team,

When running the “enet_lwip_icssg” use cases provided by the “mcu_plus_sdk_am64x_08_04_00_17” on the AM64XEVM board, I found that UDMA could not trigger interruptions, and NIC’s reception of data packets completely depended on the triggering of the timer. Could you please tell me how to solve this? My test method was adding flag bits to the interruption handler and modifying the trigger time of the timer to determine whether the interruption was triggered or not.

Kind regards,

Katherine

over 2 years ago

0 Katherine Wang over 2 years ago

TI__Intellectual 2210 points

Hello,

Could you please follow up on my issue?

Regards,

Katherine

0 Ashwani Goel over 2 years ago in reply to Katherine Wang

TI__Mastermind 27310 points

Hi Katherine,

Sorry for delay in response.

I will try to reproduce the issue and come back.

Best Regards

Ashwani

0 Ashwani Goel over 2 years ago in reply to Ashwani Goel

TI__Mastermind 27310 points

I installed "mcu_plus_sdk_am64x_08_04_00_17" at "C:\ti\mcu_plus_sdk_am64x_08_04_00_17"

Installed CCS12 at "C:\ti\ccs1200"

Import "C:\ti\mcu_plus_sdk_am64x_08_04_00_17\examples\networking\lwip\enet_lwip_icssg\am64x-evm\r5fss0-0_freertos\ti-arm-clang"

Configure board using SBL NULL.

Build and load application, I ma getting below log. Can you please confirm if we are on same page or difference from your setup ?

=====================================================================

Starting NULL Bootloader ...

DMSC Firmware Version 8.4.7--v08.04.07 (Jolly Jellyfi
DMSC Firmware revision 0x8
DMSC ABI revision 3.1

INFO: Bootloader_runCpu:155: CPU r5f1-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU r5f1-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU m4f0-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU a530-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU a530-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runSelfCpu:217: All done, reseting self ...

==========================
ENET LWIP App
==========================
Enabling clocks!
Mdio_open: MDIO Manual_Mode enabled
EnetPhy_bindDriver: PHY 15: OUI:080028 Model:0f Ver:01 <-> 'dp83869' : OK
PHY 3 is alive
PHY 15 is alive
Starting lwIP, local interface IP is dhcp-enabled
Host MAC address: 70:ff:76:1e:9c:a8
[LWIPIF_LWIP] Enet has been started successfully
[LWIPIF_LWIP] NETIF INIT SUCCESS
status_callback==UP, local interface IP is 0.0.0.0
UDP server listening on port 5001
Icssg_handleLinkUp: icssg1-1: Port 1: Link up: 1-Gbps Full-Duplex
link_callback==UP
5.147s : CPU load = 2.50 %
10.147s : CPU load = 2.11 %
15.147s : CPU load = 2.10 %
20.147s : CPU load = 2.10 %
25.147s : CPU load = 2.10 %
30.147s : CPU load = 2.10 %
35.147s : CPU load = 2.11 %
40.147s : CPU load = 2.11 %
45.147s : CPU load = 2.10 %
50.147s : CPU load = 2.10 %
55.147s : CPU load = 2.10 %
60.147s : CPU load = 2.10 %
65.147s : CPU load = 2.10 %
70.147s : CPU load = 2.11 %
75.147s : CPU load = 2.11 %
80.147s : CPU load = 2.11 %
85.147s : CPU load = 2.10 %
90.147s : CPU load = 2.10 %
95.147s : CPU load = 2.10 %
100.147s : CPU load = 2.10 %
105.147s : CPU load = 2.10 %
110.147s : CPU load = 2.10 %
115.147s : CPU load = 2.10 %
120.147s : CPU load = 2. 9 %
125.147s : CPU load = 2.10 %
130.147s : CPU load = 2.11 %
135.147s : CPU load = 2.10 %
140.147s : CPU load = 2.10 %
145.147s : CPU load = 2.11 %
150.147s : CPU load = 2.11 %
155.147s : CPU load = 2.11 %
160.147s : CPU load = 2.11 %
165.147s : CPU load = 2.10 %
170.147s : CPU load = 2.11 %
175.147s : CPU load = 2.11 %
180.147s : CPU load = 2.11 %
185.147s : CPU load = 2.11 %
190.147s : CPU load = 2.11 %
195.147s : CPU load = 2.10 %
200.147s : CPU load = 2.10 %
205.147s : CPU load = 2.10 %
210.147s : CPU load = 2.10 %
215.147s : CPU load = 2.10 %
220.147s : CPU load = 2.11 %
225.147s : CPU load = 2.11 %
230.147s : CPU load = 2.10 %
235.147s : CPU load = 2.10 %
240.147s : CPU load = 2.10 %
245.147s : CPU load = 2.10 %
status_callback==UP, local interface IP is 169.254.169.156
250.147s : CPU load = 2.13 %
255.147s : CPU load = 2.11 %
260.147s : CPU load = 2.10 %

=====================================================================

Best Regards

Ashwani

0 Katherine Wang over 2 years ago in reply to Ashwani Goel

TI__Intellectual 2210 points

Hi Ashwani,

The customer replied he could load and print smoothly, but during the test, he found that during the process of sending and receiving packets, rxPacketSemObj in the function Lwip2Enet_rxPacketTask completely depended on Lwip2Enet_timerCb for V operation, while Lwip2Enet_notifyRxPackets was not called at all. Meanwhile, by printing the register, he found the register corresponding to Interrupt Aggregator and GICSS0_SPI was enabled, but the interrupt was not triggered.

Regards,

Katherine

0 Ashwani Goel over 2 years ago in reply to Katherine Wang

TI__Mastermind 27310 points

They are using java-script or SBL to initialize board ?

Best Regards

Ashwani

0 Katherine Wang over 2 years ago

TI__Intellectual 2210 points

Hi Ashwani,

tarting NULL Bootloader ... 

DMSC Firmware Version 8.4.7--v08.04.07 (Jolly Jellyfi
DMSC Firmware revision 0x8
DMSC ABI revision 3.1

INFO: Bootloader_runCpu:155: CPU r5f1-0  is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU r5f1-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU m4f0-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU a530-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU a530-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runSelfCpu:217: All done, reseting self ...

==========================
      ENET LWIP App       
==========================
Enabling clocks!
Mdio_open:282 
EnetPhy_bindDriver:1718 
PHY 3 is alive
PHY 15 is alive
Starting lwIP, local interface IP is dhcp-enabled
Host MAC address: 70:ff:76:1e:2a:d9
[LWIPIF_LWIP] Enet has been started successfully
[LWIPIF_LWIP] NETIF INIT SUCCESS
status_callback==UP, local interface IP is 0.0.0.0
UDP server listening on port 5001
      5.135s : CPU load =   1.17 %
     10.135s : CPU load =   0.58 %
     15.135s : CPU load =   0.48 %
     20.135s : CPU load =   0.59 %
     25.135s : CPU load =   0.49 %
     30.135s : CPU load =   0.58 %
     35.135s : CPU load =   0.59 %
     40.135s : CPU load =   0.48 %
Icssg_handleLinkUp:2495 
link_callback==UP
status_callback==UP, local interface IP is 192.168.18.125
     45.135s : CPU load =   0.63 %
     50.135s : CPU load =   1.34 %
     55.135s : CPU load =   1.66 %
IPERF report: type=0, remote: 192.168.18.32:10730, total bytes: 1048600, duration in ms: 9200, kbits/s: 904

The code above is the printed information the customer configured with SBL NULL, and there is no distinct difference from your setup. The result of the iperf speed measurement below is caused by extending the trigger interval of the timer. During the test, it was found that during the process of sending and receiving packets, the rxPacketSemObj in the function Lwip2Enet_rxPacketTask completely depended on the V operation performed on Lwip2Enet_timerCb, while Lwip2Enet_notifyRxPackets was not called at all. At the same time, by printing the registers, it was found that the register corresponding to Interrupt Aggregator and GICSS0_SPI was enabled, but the interrupt was not triggered.

Kind regards,

Katherine

0 Ashwani Goel over 2 years ago in reply to Katherine Wang

TI__Mastermind 27310 points

Hi Katherine,

I will check this with my dev team and come back.

Best Regards

Ashwani

0 Katherine Wang over 2 years ago

TI__Intellectual 2210 points

Hi Ashwani,

The customer replied that he had tried using javascript and programing SBL initialization, but he got the same results in these two cases after testing.

Regards,

Katherine

0 Ashwani Goel over 2 years ago in reply to Katherine Wang

TI__Mastermind 27310 points

Thanks for update Katherine.

I still doubt there is some difference test case I am running and customer side.

Is it possible to share customer test code with us. So that I can run same on my setup ?

Best Regards

Ashwani

0 Ashwani Goel over 2 years ago in reply to Ashwani Goel

TI__Mastermind 27310 points

Hi Katherine,

The reason of using Lwip2Enet_timerCb instead of UDMA interrupts to receive packet is solely because Interrupt aggregator does not support interrupt pacing, and we will see performance degrade if change this logic. Though functionality should not get impacted.

Best Regards

Ashwani

0 Katherine Wang over 2 years ago

TI__Intellectual 2210 points

Hi Ashwani,

The code the customer used is the routine under the mcu_plus_sdk_am64x_08_04_00_17\examples\networking\lwip\enet_lwip_icssg path. He said if you needed to test the code, the easiest way was to make modifications to the Lwip2Enet_createTimer function (line 1474) under source\networking\enet\core\lwipif\src\V1\lwip2enet.c, making the following changes to and recompiling clkPrms.timeout and clkPrms.period. The issue observed is that when using iperf for testing, the customer found the performance dropped significantly.

static void Lwip2Enet_createTimer(Lwip2Enet_Handle hLwip2Enet)
{
    ClockP_Params clkPrms;
    int32_t status;

    ClockP_Params_init(&clkPrms);
    clkPrms.start  = true;
    clkPrms.timeout = 100/* ClockP_usecToTicks(hLwip2Enet->appInfo.timerPeriodUs) */;
    clkPrms.period = 100/* ClockP_usecToTicks(hLwip2Enet->appInfo.timerPeriodUs) */;
    clkPrms.callback = &Lwip2Enet_timerCb;
    clkPrms.args = hLwip2Enet;

    status =  ClockP_construct(&hLwip2Enet->pacingClkObj, &clkPrms);
    Lwip2Enet_assert(status == SystemP_SUCCESS);
}

Kind regards,

Katherine

0 Ashwani Goel over 2 years ago in reply to Katherine Wang

TI__Mastermind 27310 points

Hi Katherine,

An Update:

In case of AM64x (UDMA), we are supporting SW interrupt interrupt pacing.

But, we do not support hybrid (SW timer + HW timer).

Best Regards

Ashwani

0 Katherine Wang over 2 years ago in reply to Ashwani Goel

TI__Intellectual 2210 points

Hi Ashwani,

For the enet_lwip_icssg routine, how should it be modified to support udma hardware interrupts? The software timer used in the routine comes with the product, not added by me.

Regards,

Katherine

0 Ashwani Goel over 2 years ago in reply to Katherine Wang

TI__Mastermind 27310 points

Hi Katherine,

I will check if there is some existing example for this and share with you.

Best Regards

Ashwani

0 Katherine Wang over 2 years ago in reply to Katherine Wang

TI__Intellectual 2210 points

Katherine Wang said:
For the enet_lwip_icssg routine, how should it be modified to support udma hardware interrupts? The software timer used in the routine comes with the product, not added by me.

Hi Ashwani,

The customer inquired what modifications he could make to the enet_lwip_icssg routine so that it could support hardware interrupts. Could you please follow up on this?

Regards,

Katherine

0 Ashwani Goel over 2 years ago in reply to Katherine Wang

TI__Mastermind 27310 points

Hi Katherine,

Can you check and confirm below function:
- Lwip2Enet_Handle Lwip2Enet_open(struct netif *netif)

have

- EnetDma_disableRxEvent(hLwip2Enet->rx[i].hFlow);

and

- EnetDma_enableRxEvent(hLwip2Enet->rx[i].hFlow);

There is similar ones for Tx also..
These API's are to enable to disable HW events.

Best Regards

Ashwani

0 Katherine Wang over 2 years ago in reply to Ashwani Goel

TI__Intellectual 2210 points

Hi Ashwani,

The customer replied that by modifying LwipifEnetAppCb_getHandle function, namely changing the value of rx/txInfo.disableEvent to false and enabling event in Lwip2Enet_open, the interrupts could be triggered smoothly.

Regards,

Katherine

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AM6442: UDMA failed to trigger interruptions