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what each peripheral clock input is for TMS320C6455

Vish
Prodigy 70 points

Other Parts Discussed in Thread: TMS320C6455

What is the frequency of clock that is being fed into the Timer 0 and Timer 1 peripheral timers on the TMS320C6455? I am not able to find the right document that describes the clocking of the entire chip. I can find the individual register definitions but not what each peripheral clock input is.

  • 0
    TI__Intellectual 1920 points

    In the document - http://focus.ti.com/lit/ds/symlink/tms320c6455.pdf, page 132,  states the SYSCLK3 clocks the TIMER.  The frequency will be determined by the value chosen for the dividers.

  • 0
    TI__Guru* 84110 points

    To reach all of this information, you can start from www.ti.com and fill in the "Search by Keyword" at the top with C6455. The product folder will usually be one of the first items in the returned list, or you can click Active Product Folders on the left pane to bring the product folder closer to the top. Clicking on the product folder link will bring up a page with "all" the available information on the device. Click on Technical Documents to get to the good stuff for engineers.

     

    In additiona to what Devin explains, the datasheet (spru276h) has details on connection trees within the chip, including the clocking trees. In Chapter 7 "C64x+ Peripheral Information…", section 7.7 covers the PLL1 clocking tree and on page 132 is Figure 7-10 which shows the internal clock paths from the pins to the peripherals. In the text below that figure, in section 7.7.1.1, the last bullet on the page states that "SYSCLK3 clocks the … TIMER peripheral", so you can map that to Figure 7-10 to see that SYSREFCLK (the 1GHz C64x+ Megamodule core clock) goes through Divider D3 (fixed at /6) to generate SYSCLK3, which then goes to the Timers.

     

    Back to the Product Folder, under Technical Document is also User Guides where the 64-Bit Timer User's Guide is located, currently spru968 (new revisions may be published from time-to-time). On page 10, Figure 1 shows the Timer Block Diagram which includes the logic to control and select the clock to the Timer. "Internal clock" means SYSCLK3 for the C6455, but you can also choose to gate that internal clock using the TINPL pin, or you can choose to use the TINPL pin as a direct external clock to the timer. Figure 2 on the next page does not look like it provides a lot of information at first, but it does point out that there is a prescaler available for the Timer, depending on how you choose to configure the Timer.

     

    If you use the TINPLx pin(s) as an external clock, you will need to go back to the datasheet to determine the maximum clock rate. In section 7.15.3 on page 214, the minimum pulse width for TINPLx being high or low is 12P, or 12ns for your case of a 1GHz CPU clock frequency. With TINPLx-high + TINPLx-low = 12 + 12 = 24 ns, the maximum external clock frequency is 1/24 ns = 41.6 MHz. Or with the internal clock, you would have 1000/6 MHz = 166.6 MHz.