AM62A7: How to use CCS setup for AM62A

Hi team,

 Because we can't boot by SD card , so I'd like to know how to load the image by JTAG to boot it. could you give us some guides?

Hi team,

Currently, we skip SD card and power up, then connect JTAG and CCS, we just find SMS core is active, how to setup for AM62A base on that condition.

Hi team,

 Now we can active most of cores in AM62A(as below), but it's failed when we follow the guide(as below) to load spl file, that as below picture(we have tried

u-boot_build/r5/spl/u-boot-spl and u-boot_build/a53/spl/u-boot-spl). So we think the guide is not correctly, and we'd like to know which file will to be load and run which core, that file be producted by which source code? 

load failed log:

CCS status:

guide:

Hi Cary,
I'm attaching AM62x boot flow slide for your reference, where boot process is similar on AM62x/AM62A. On K3 SoC (i.e. AM62A, AM62x, AM64x...), u-boot/Linux boot is a multi-stage boot process across multiple cores, which makes loading/debugging the multi-stage boot binaries with JTAG is a non-trivial process. You may also refer to Linux SDK boot flow diagram here
https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/08_05_00_21/exports/docs/linux/Foundational_Components/U-Boot/UG-General-Info.html#boot-flow

Some recommendations for you to debug the non-working boot issue on the customer board:
1. add a spin loop when building R5 SPL
2. boot the newly built R5 SPL, u-boot... on your board
3. "attach" JTAG to the running board, where "attach" is non-intrusive to the running board or NO HW RESET (don't run any GEL script...)
4. break, and review disassembly, PC... with JTAG to see if the breaked code is in a/. bootrom OR b/. the "spin" loop added in R5 SPL.
5. check your HW board etc...if 4a/ or debug your R5 SPL... if 4b/.

I'm also attaching T32 screenshot with the "spin" loop added in R5 SPL on AM64x EVM for your reference.

Best,
-Hong

6082.AM62x_Boot_Overview_v3.pdf

Hi Hong,

Thanks a lot!

And I'd like you know what cause we loaded spl.bin by CCS, could tell what's the reason for the loading fail from error log.

Hi Hong,

3. "attach" JTAG to the running board, where "attach" is non-intrusive to the running board or NO HW RESET (don't run any GEL script...)

    -->If we don't run GEL script, it just active SMS core, the other core are disconnected, as below picture. So we can't load SPL.

Only run GEL script that most cores connected, now we load SPL based on run the script, but loading spl fail 

Hi Cary,
Additional note on my reply:
“attach” is attaching JTAG to R5 core, but don’t run any GEL script.
I use Lauterbach T32 JTAG for “attach”, but I’m pretty sure “attach” is also supported in CCS.
Best,
-Hong

Hi Hong,

 Thank you so much!

 We think customer's board power up is not properly from your guide and current issue status.

Hi Hong,

We test on UART mode, the serial terminal can print a long string, so we think SOC power up properly. But back to no boot mode, don’t run GEL script, all ores are disconnect. 

Hi Hong,

 We meet the key issue is that "attach" JTAG to the board, the R5 core is inactive, so we can't load the SPL file.

Hi Hong,

 I'd like to know what's the condition of the board can attach JTAG, it can attach after SOC run ROM code?