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TDA4VM: Why does VISS impact SPI communication on R5F2_1?

user6314500
Intellectual 460 points
Part Number: TDA4VM


Hello Supporter,

===================================================================================

Basic information:

(1) HW: TDA4VM with custom board

(2) SW: SDK 7.3

===================================================================================

we are using 3 ch SPI on R5F2_1 for USS communication. And each SPI will read 52 bytes of data from USS sensor every 1ms. The SPI communication is interruption way.

But we get an issue that When the VISS is running, just 32 Bytes (expected 52 bytes) of data are received. And the SPI communication is working normal when the VISS is stop.

After analysis, we find that the SPI FIFO size is 32 Bytes. So, we make the change that extend the SPI data package to 64 Bytes (twice of the FIFO size). The SPI communication is improved. But there are still some SPI data getting lost when the VISS is running.  

So, we still think the VISS impact the SPI communication.

Could you please double confirm is there any known issue about the VISS and SPI? Or is there any special configurations about VISS and SPI?

 

Best Regards,

Jingchun Li

  • 0
    TI__Guru**** 480825 points

    Hi Jingchun Li,

    Are you using DMA mode for the SPI communication? 

    As such, VISS and SPI are completely independent modules and VISS should not affect SPI communication.. 

    Can you please provide some more information about SPI configuration? 

    - Which SPI instance are you using?

    - Are you using SPI in interrupt mode or polling mode?

    - Are you using DMA for SPI communication? 

    - What is the SPI FIFO trigger level?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 460 points

    Hello Brijesh,

    Are you using DMA mode for the SPI communication? 

    Jingchun: No, SPI Interrupt Mode is used.

    As such, VISS and SPI are completely independent modules and VISS should not affect SPI communication.. 

    Can you please provide some more information about SPI configuration? 

    - Which SPI instance are you using?

    Jingchun: The SPI0, SPI1and SPI2 of the MAIN domain are used.

    - Are you using SPI in interrupt mode or polling mode?

    Jingchun:  SPI is used in interrupt mode.

    - Are you using DMA for SPI communication? 

    Jingchun: No, not using DMA for SPI.

    - What is the SPI FIFO trigger level?

    Jingchun:  SPI FIFO trigger level is 32 Bytes

    ====================================================================================

    Is there any possibale that the VISS interrupt rountine impacts the SPI intterrupt rountine?

    Is there any specail configuraton about VISS and SPI interrupt?

     

    Best regards,

    Jingchun Li

  • 0 in reply to user6314500
    TI__Guru**** 480825 points

    Hello Jingchun Li,

    Sorry for the late reply. 

    VISS uses irq number 34, as per ti-processor-sdk-rtos-j721e-evm-07_03_00_07\pdk_jacinto_07_03_00_29\packages\ti\drv\vhwa\soc\V0\vhwa_soc.h. Also SPI0 and SPI1 has direct irq line to the R5F, ie irq 152 and 153, so SPI0 and SPI1 cannot interfere with VISS and vice versa. 

    But for SPI2, there is no direct interrupt to R5F, so you need to configure R5F interrupt router and select one free irq number. Now if you are by mistake using same irq number as VISS, it can potentially affect. 

    So, can you please first check

    - if you use only SPI0 and SPI1, there is no issue

    - what irq number if used for SPI2 and if it is same as VISS irq number 34.

    Regards,

    Brijesh