• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 100 subscribers
  • Views 432 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SK-TDA4VM: MCU domain turns on the issue of dual-core data consistency

Cherry Zhou
Mastermind 22235 points

Part Number: SK-TDA4VM
Other Parts Discussed in Thread: TDA4VM

Hi team,

Here's an issue from the customer may need your help:

When using the TDA4VM chip, turn on the dual-core mode with R5FSS from MCU domain and place the data in DDR. It is now found that using write back can significantly reduce CPU loading, but there is a problem with data inconsistencies. Which portion of the data is shared between the dual cores? 

Since there is more shared data and a larger data type, the customer want to be able to use Cache to reduce CPU load and improve read and write efficiency. So they would like to know is there a way to use Cache while still maintaining data consistency? For example,

1) whether the MESI protocol or MOESI protocol is supported.

2) whether there is a function interface that allows manual clearing of the cache section.

3) Can block zones be set to other modes than Cacheable and No cache? For example, the out-shareable mode.

Best Regards,

Cherry

  • 0
    TI__Mastermind 22235 points

    Hi,

    May I know any updates here?

    Thanks and regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Guru** 120475 points

    Hi Cherry,

    The R5F Core0 and Core1 (MCU or MAIN) are not Cache Coherent w.r.t. each other. There is no common Cache, and a s/w cache coherence (regular flush and invalidate depending on the direction of buffer/data) methodology should be used. Each of the Core0 and Core1 have their own Memory Protection Unit (MPU), which is the module used for Cache configuration.  

    There is no data sharing between the two cores by default, the memory in DDR would be a Shared Memory concept, and you would have to configure both the MPUs accordingly. Please look at the R5F Block Diagram in the TRM, that should give you an idea of the h/w architecture.

    The Cache Write-Back mode definitely incurs performance penalty compared to a Cached buffer. You would want to use cacheable buffers in general, and then once the access is done, perform a cache flush or invalidate depending on the write or read operation. 

    The MPU used is the standard ARM Cortex-R5 MPU, please look through the ARM v7R TRM for details on various settings allowed.

    regards

    Suman