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AM4376: Internal I/O circuitry

Kanae
Guru 10245 points

Part Number: AM4376

Hi Support Team,

Our customer has the following questions about the internal I/O circuitry of AM4376.

Q1. Refer to the pin setting register "CTRL_CONF_GPMC_A0" of C3 pin GPMC_A0 of AM437x,
 and you will find the following descriptions in Bit 16 to 18, which enable/disable the Receiver,
 select internal pullup/pulldown, and enable/disable their settings.


Thus, the AM437x pin setting register has an enable/disable setting for the Receiver,
but does not seem to have an enable setting for the Transceiver.

Q1-1: Am I correct in understanding that the Transceiver is always routed to the IO port on the AM437x IO pins?

Q1-2. Also, if RXACTIVE=0 and receiver disabled, it seems to me that the connection from outside IO port
 to internal input buffer is disconnected, but is this understanding correct?

Q2.
Q2-1. If the following pin settings are made, what state will the IO port be in?

 Set "0x 0801 0007" for the register setting "CTRL_CONF_GPMC_A0
 CONF_GPMC_A0_RXACTIVE =0 receiver disabled
 CONF_GPMC_A0_PUTYPESEL =0 Pulldown selected
 CONF_GPMC_A0_PUDEN =1 Pullup / Pulldown disabled
 Pad Functional Signal Mux Select=7 GPIO1_16

Q2-2. In addition to the above, GPIO1_16 is applicable in the register setting of GPIO.
 GPIO_OE =1 GPIO port is configured as an input.
 CTRL_CONF_GPMC_A0 disables the Receiver, but if GPIO_OE is configured as an input port
 without selecting output, will it be in IO port Hi-Z output state?


Q3. Regarding the setting of unused pins, in 2.1 of the document "AM437x schematic checklist
 Unused pins can be left unconnected, and it is recommended to set RXACTIVE=0 to suppress leakage current.
 Related to Q1 and Q2, if unused pins are to be left unconnected, what settings other than RXACTIVE=0 should be used?
 Is it OK to use the setting in Q2?

Best Regards,
Kanae

  • 0
    TI__Guru**** 215910 points

    Hello Kanae,

    Thank you for the query.

    Kanae said:
    Thus, the AM437x pin setting register has an enable/disable setting for the Receiver,
    but does not seem to have an enable setting for the Transceiver.

    Please point me to the Transceiver you mentioned. above.

    Can you please some background or the use case. Based on the use case i will have to assign to the expert.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Guru 10245 points

    Hi Sreenivasa,

    Thank you for your reply.

    The following is an example of customer use and some background on the question.


    Our model currently under development uses two AM437x.
    (*Pin assignments and usage methods are different.)
    The usage of each chip as "CPU A" and "CPU B" is described below.

    -How to use CTRL_CONF_GPMC_A0 with "CPU A
    Since the C3 pin (default pin name: gpmc0) is not used in "CPU A",
    it is assumed to have no connection point (float) on the board.
    The current register settings for CTRL_CONF_GPMC_A0 and GPIO are as described in "Q2" .
    I would like to confirm if there is a problem with this setting.
    I would also like to know the state of the pins at this time (output state or Hi-Z state?).


    -How to use CTRL_CONF_GPMC_A0 in "CPU B
    In "CPU B", there are cases where the C3 pin has a destination device (LAN PHY IC) or not,
    depending on the specifications.
    The software will be configured according to the specifications, and the CTRL_CONF_GPMC_A0
    setting will be changed.

    -In case of this pin is implemented
    This pin is used as rmii2_txen, so CTRL_CONF_GPMC_A0 should be set to "0x 0801 0003".

    -In case of this pin is not implemented
    This pin has no device to be connected to (float), although the pattern is drawn out.
    CTRL_CONF_GPMC_A0 is set to "output" state, and I plan to set it to GPIO to fix "L" output.

    ■Background of questions
    Other developers in our company have given us the following information.
    In the example of other CPUs, IO pins are normally set as input settings,
    so unused pins should be set to default input settings.
    If there is an internal PU/PD setting, set this to PD and so on to fix the logic.

    *Of course, if the IC has a specification on how to handle unused pins, follow it.

    For this CPU AM437x, the document "AM437x schematic checklist" 2.1 recommends
    RXACTIVE=0 is recommended in the document "AM437x schematic checklist"
    for this CPU AM437x, so RXACTIVE=0 is set in this model development.

    In order to confirm that this setting is OK, I wanted to know the state of the IO pin
    when the setting is as described in "Q2" in the previous post.

    Also, I would like to understand the internal circuit structure of the IO pins correctly.
    If possible, please explain the image of the internal circuit structure of AM437x.

    Best Regards,
    Kanae

  • 0 in reply to Kanae
    TI__Guru**** 215910 points

    Hello Kanae, 

    Thank you for the inputs.

    Let me review the inputs.

    Please note that the device expert is on vacation this week and expect delay in response.

    Kanae said:
    Also, I would like to understand the internal circuit structure of the IO pins correctly.
    If possible, please explain the image of the internal circuit structure of AM437x.

    I am not sure on the availability and will have to check internally.

    Would you mind having this in a separate E2E for me to assign to the right experts.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Guru 10245 points

    Hi Sreenivasa,

    Thank you for your reply.
    OK, I will post the following questions in a new thread.

    Also, I would like to understand the internal circuit structure of the IO pins correctly.
    If possible, please explain the image of the internal circuit structure of AM437x.

    Best Regards,
    Kanae

  • 0 in reply to Kanae
    TI__Guru**** 215910 points

    Hello Kanae, 

    Noted and Thank you.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru 63875 points

    I will attempt to answer your original questions below:

    Q1-1:
    I assume you are asking about the IO output buffer with your reference to transceiver. I suspect this is your way of asking how the output buffer is enabled or disabled. The output enable of each IO is routed through the pin mux logic and connects to the respective peripheral module based the MODE value. For example, if the GPIO signal function is selected the output enable will be sourced by the GPIO module. The AM437x device does not have a TXDISABLE bit equivalent to the RXACTIVE bit.

    Q1-2:
    The input buffer is turned off and the input path through the IO cell is disconnected when the IO receiver is disabled with the RXACTIVE bit.  AM437x pins should never be allowed to float to mid-supply voltages when the receiver is enabled.  The pin can float when disabled.  However, the receiver associated with most pins are turned on by default as soon as the device is powered-up.  Most of these pins also have an internal pull turned on by default as soon as the device is powered-up.  You should check the default state of each pin that is defined in the Pin Attributes section of the datasheet.  See the BALL RESET STATE and BALL RESET REL. STATE columns of the Pin Attributes table.

    Q2-1:
    The input path is disconnected, the internal pulls are turned off, and the GPIO signal function is selected.  Refer to the Pin Attributes section of the datasheet for more information on signal functions available on each pin.  See the SIGNAL NAME and MODE columns of the Pin Attributes table.

    Q2-2:
    The pin will be in Hi-Z state if the GPIO signal function is selected via the MODE bits in the pad configuration register and the respective GPIO_OE bit in the GPIO module disables the output buffer. The state of RXACTIVE has no influence on the operation of the output buffer.

    Q3:
    The AM437x schematic checklist assumes each unused pin will have an internal pull turned on by default.  The internal pull will attempt to hold the pin in a valid logic state.  Turning off the input buffer with the RXACTIVE bit helps to eliminate any leakage current through the input buffer if noise couples to the unused pin and over-drives the internal resistor, which forces the input to a mid-supply potential.  This is very unlikely to happen if do not connect any signal traces to unused pins.  Connecting signal traces to unused pins is not recommended since they can act like antennas and pick-up noise that can over-drive the internal resistor and force the input to a mid-supply potential.

    Regards,
    Paul

  • 0 in reply to peaves
    Guru 10245 points

    Hi Paul,

    Thank you for your support.

    I will share it with my customer.

    Best Regards,
    Kanae 

  • 0 in reply to Kanae
    TI__Guru**** 215910 points

    Hello Kanae,

    Thank you for the note.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Guru 10245 points

    Hi Paul,

    After sharing the answers with the customer, Q1. Q2 is understood, and closed is fine.
    For Q3, there are additional questions.


    Q3-1.
    If the "internal resistor" mentioned here refers to the internal pull resistor that is enabled by default,
    am I correct in understanding that for unused pins, in addition to RXACTIVE=0,
    it is recommended to disable the internal pull (or leave the signal line unconnected)?
    I understand that there is no concern about leakage current due to noise
    if the signal line is not connected to unused pins originally,
    but there are cases where a pattern is connected to separate specifications like "CPU B" explained
    in the previous post, or a check pad is provided for debugging purposes. 
    In such a case, if RXACTIVE=0 and internal pull is disabled, is it possible to eliminate the concern of intermediate potential due to noise and the resulting leakage current in the input buffer?

    Q3-2.
    Please let me confirm this just to be sure.
    Regarding your previous question in Q3, is it correct to say that
    the following settings described in "Q2" for unused pins are OK?

    CONF_GPMC_A0_RXACTIVE =0 receiver disabled
    CONF_GPMC_A0_PUTYPESEL =0 Pulldown selected
    CONF_GPMC_A0_PUDEN =1 Pullup / Pulldown disabled
    Pad Functional Signal Mux Select=7 GPIO1_16

    Best Regards,
    Kanae

  • 0 in reply to Kanae
    TI__Guru 63875 points

    Q3-1:
    There is no significant difference in leakage current as long as the input buffer is disabled. It doesn't matter if the internal pull is turned on or off. However, you must never turn off the internal pull while the input buffer is still enabled unless the pin is driven or pulled to a valid logic state by an external component. I recommend leaving the internal pull turned on to prevent any risk of an Electrical Over Stress (EOS) event.

    There is some risk that an unused signal trace connected to a pin could allow noise to induce a voltage potential. Any signal trace connected to a pin that is not driven or pulled to a valid logic state will be very high impedance, which makes it easy for noise to induce a voltage potential that could exceed the maximum voltage rating for the pin. The internal pull or an external pull would provide a current path for the induced noise which will minimize the voltage potential that is applied to the pin.

    Q3-2
    As mentioned above, I would leave the internal resistor turned on.

    Regards,
    Paul

  • 0 in reply to peaves
    Guru 10245 points

    Hi Paul,

    Thank you for your support.

    Regarding your answer to Q3-2, please let me check again.
    You answered Q3-1 that if the input buffer is disabled (CONF_GPMC_A0_RXACTIVE = 0),
    there is no need to enable the internal pull, but your answer to
    Q3-2 (I would leave the internal resistor turned on.) seems contradictory. 

    CONF_GPMC_A0_RXACTIVE =0 receiver disabled
    CONF_GPMC_A0_PUTYPESEL =0 Pulldown selected
    CONF_GPMC_A0_PUDEN =1 Pullup / Pulldown disabled
    Pad Functional Signal Mux Select=7 GPIO1_16

    Is there a problem with the above configuration and should I modify it as follows?

    CONF_GPMC_A0_RXACTIVE =0 receiver disabled
    CONF_GPMC_A0_PUTYPESEL =0 Pulldown selected
    CONF_GPMC_A0_PUDEN =0 Pullup / Pulldown enabled
    Pad Functional Signal Mux Select=7 GPIO1_16

    Sorry to keep repeating this, but please allow me to confirm it.

    Best Regards,
    Kanae

  • +1 in reply to Kanae
    TI__Guru 63875 points

    My previous answer applied to the use case where a pin did not have any signal trace connected. My last reply was addressing the case where you have a PCB signal trace connected.  It is very unlikely for noise to couple energy to an unconnected pin. That is not the case for a long signal trace. A long signal trace needs either the internal pull or an external pull to hold in a valid logic state.

    Regards,
    Paul

  • 0 in reply to peaves
    Guru 10245 points

    Hi Paul,

    Thank you for your support!

    I will share it with my customer.

    Best Regards,
    Kanae 

  • 0 in reply to Kanae
    TI__Guru**** 215910 points

    Hello Kanae,

    Thank you for the note.

    Regards,

    Sreenivasa