I'd like to design a system based on the AM4372 SOC.
I'd like the GPMC bus to be clocked with an external oscillator that has a frequency of 43.75 MHz.
Does this device support that ?
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I'd like to design a system based on the AM4372 SOC.
I'd like the GPMC bus to be clocked with an external oscillator that has a frequency of 43.75 MHz.
Does this device support that ?
Hello Shai Kon
Thank you for the query.
Please provide some additional details on the required and add a simple block diagram showing the interface.
Regards,
Sreenivasa
Hi.
What I'd like to know is whether the GPMC clocked by an external clock pin at 43.75MHz
Hello Shai Kon
Thank you.
You are looking to add an external clock that drives the processor and the attach device.
This clocking approach you have shown does not seem to be feasible.
Pls help me understand the use case and if some analysis has been done from your side on the pins that you would want to connect the clock both on the processor side and the device side.
Regards,
Sreenivasa
I'm not trying to add anything...
I'm asking what clock sources on the AM4372 device can be used to drive the CPU's GPMC ?
Can it be an external oscillator ? If yes, can it be 43.75 MHz ?
If the answer is no - can you please point me to a document that describes the clock tree of the AM4372 ?
Hello Shai Kon
Thank you.
As quick reference please ref the Data sheet, TRM - below sections.
Chapter 6
Power, Reset, and Clock Management (PRCM)
7.3 Registers 7.3.1 CONTROL_MODULE Registers
9.1 GPMC 9.1.1 Introduction
If you are able to share your use case or provide the requirements, i can check internally if additional info is available that can be shared.
Regards,
Sreenivasa
Hello Shai Kon
As i said above, This clocking approach you have shown does not seem to be feasible.
Can it be an external oscillator ? If yes, can it be 43.75 MHz ?
regards,
Sreenivasa
I see. Can you please point me to a document describing the clocking options for the GPMC ?
Hi Shai,
Short answer is no the GPMC cannot take in an external clock source as its reference clock. Its only clock source comes through the core PLL and HSDIVIDER. OSC0 is limited to 19.2-MHz, 24-MHz, 25-MHz, or 26-MHz. The PLL could be bypassed, but core will run very slowly (more for low power modes).
The only clock source available to the GPMC_FCLK is pd_per_l3s_gclk which equals CORE_CLKOUTM4 / 2. This clock is typically 100MHz, but configurable by adjusting HSDIVIDER M4 divider. Note that multiple other peripherals also derive their clocks from this output clock and you may break their functionality by adjusting it!
Additionally, the GPMC_CLK pin is an output only from the processor. You cannot use an external input.
Refer to TRM Table 9-3. GPMC Clock Signals
and TRM Figure 6-14. Core PLL Structure
TRM link: https://www.ti.com/lit/pdf/SPRUHL7
You can also dive into the clocks of AM437x using the Clock Tree Tool
- See https://www.ti.com/tool/CLOCKTREETOOL
- download CLOCKTREETOOL-SITARA
- Requires Java Runtime Engine such as JDK v202 (last free version)
- Once installed, run CTT-Sitara-Legacy.jar
Hope this helps,
Mark