AM62A7: PMIC warm reset occurs when voltage switching is enabled.

Vinay S

Part Number: AM62A7
Other Parts Discussed in Thread: TPS6593-Q1

Hi,

We are testing AM62A7 based custom board with SDK 9.0.0.

If voltage switching is enabled for Micro SD and Micro SD is inserted then board is resetting when initializing SD card.

We tried to read the registers and confirmed 0x83(RECOV_CNT_REG_1) offset under 0x48(PMIC slave address) gets incremented when board is reset.

Under what cases does the PMIC warm reset occurs and how to debug this issue further?

over 1 year ago

0 Vinay S over 1 year ago

Intellectual 365 points

One more observation we found is when setting LDO1 voltage to 1.8V in device tree board resets after setting the LDO1 to 1.8V.

Below are the prints before the board resets.

[ 1.733199] vddshv5_sdio: Bringing 3300000uV into 1800000-1800000uV
[ 1.734185] mmcblk0: p1 p2

0 Kallikuppa Sreenivasa over 1 year ago

TI__Guru**** 188979 points

Hello Vinay,

Thank you for the query.

Vinay S said:
We are testing AM62A7 based custom board with SDK 9.0.0.

If voltage switching is enabled for Micro SD and Micro SD is inserted then board is resetting when initializing SD card.

Please share the information on the PMIC that you are using.

Vinay S said:
If voltage switching is enabled for Micro SD and Micro SD is inserted then board is resetting when initializing SD card.

We tried to read the registers and confirmed 0x83(RECOV_CNT_REG_1) offset under 0x48(PMIC slave address) gets incremented when board is reset.

Under what cases does the PMIC warm reset occurs and how to debug this issue further?

Is the PMIC resetting or the SoC resetting.

Please eloborate.

Regards,

Sreenivasa

0 Vinay S over 1 year ago in reply to Kallikuppa Sreenivasa

Intellectual 365 points

Hello,

We are using same PMIC as EVM (TPS6594) in our custom board.

PMIC is getting reset causing board reset when LDO1 voltage is switched to 1.8V

0 Kallikuppa Sreenivasa over 1 year ago in reply to Vinay S

TI__Guru**** 188979 points

Hello Vinay,

Thanks.

We are switching the LDO1 in the SK and don't see any issue - This is the VDDSHV_SDIO.

The LDO1 connections need to be verified. Please note that i do not have any implementation information to verify and suggest. I can only provide some guidelines.

Can you verify if the If the LDO1 output connects to any other 3.3V supplies. on the board.

if possible, please isolate the LDO1 supply and measure the supply voltage.

Regards,

Sreenivasa

0 Vinay S over 1 year ago in reply to Kallikuppa Sreenivasa

Intellectual 365 points

Hi,

Thanks for the reply.

We verified our board design and LDO1 output is connected only to SD power domain.

regarding SW implementation below is the changes done in device tree:

&sdhci1 {
   /* SD/MMC */
   status = "okay";
   vmmc-supply = <&vdd_mmc1>;
   vqmmc-supply = <&vddshv_sdio>;
   pinctrl-names = "default";
   pinctrl-0 = <&main_mmc1_pins_default>;
   ti,driver-strength-ohm = <50>;
//   no-1-8-v;
   disable-wp;
};

    tps659312: pmic@48 {
       compatible = "ti,tps6593-q1";
       reg = <0x48>;
       ti,primary-pmic;
       system-power-controller;

...

            ldo1: ldo1 {
               regulator-name = "vddshv5_sdio";
               regulator-min-microvolt = <3300000>;
               regulator-max-microvolt = <3300000>;
               regulator-boot-on;
               regulator-always-on;
           };

...

};

    vddshv_sdio: regulator-31 {
       compatible = "regulator-gpio";
       regulator-name = "vddshv_sdio";
       pinctrl-names = "default";
       pinctrl-0 = <&vddshv_sdio_pins_default>;
       regulator-min-microvolt = <1800000>;
       regulator-max-microvolt = <3300000>;
       regulator-boot-on;
       vin-supply = <&ldo1>;
       gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
       states = <1800000 0x0>,
           <3300000 0x1>;
   };

We have connected gpio1 15 to PMIC GPIO5 hence the change from EVK.

Also SD card is detected and working properly if voltage switching is disabled.

Also we observed a change in PMIC register LDO1_VOUT (Offset = 23h) from EVK and our board.

in EVK value of LDO1_VOUT is 0xf4 in uboot and 0x38 in kernel(after voltage switching)

in our board value is 0x74 and if we set the value to 0x38 manually using i2c commands in u-boot or kernel board is getting reset and PMIC warm reset count increases.

0 Kallikuppa Sreenivasa over 1 year ago in reply to Vinay S

TI__Guru**** 188979 points

Hello Vinay,

Refer PMIC data sheet section below

Table 8-4. Output Voltage Selection for LDO1, LDO2, and LDO3

Is there a custom NVM that was programmed on the PMIC?

Regards,

Sreenivasa

0 Vinay S over 1 year ago in reply to Kallikuppa Sreenivasa

Intellectual 365 points

Hi,

In our board design we have changed the PMIC input voltage to 5V hence disabled bypass mode for the LDO's and linear regulator mode is enabled.

We notice that in EVK when voltage switching is disabled bypass mode is enabled and after switching voltage to 1.8V bypass mode will be disabled and voltage changes to 1.8V.

In our case if voltage switching is disabled bypass mode is disabled and after switching voltage to 1.8V PMIC warm reset occurs and board resets.

On probing the LDO1 output we notice that on trying to set to 1.8V during voltage switching the voltage goes to 0 and resets the board.

Kindly find the attached OTP file for our board.

Fullscreen TPS65931211_program.txt Download

ASIL_QM=0x1
DEVICE_GPN=0x6
GRADE=0x1
TI_NVM_ID=0x11
TI_NVM_REV=0x4
CUSTOMER_NVM_ID=0x0
VMON_DEGLITCH_SEL=0x1
VCCA_VMON_EN=0x0
VCCA_OV_THR=0x7
VCCA_UV_THR=0x7
VCCA_PG_SET=0x1
VCCA_GRP_SEL=0x0
MP_CONFIG=0x3
BUCK1_EN=0x0
BUCK1_FPWM=0x1
BUCK1_FPWM_MP=0x0
BUCK1_VMON_EN=0x0
BUCK1_VSEL=0x0
BUCK1_PLDN=0x1
BUCK1_RV_SEL=0x0
BUCK1_SLEW_RATE=0x3
BUCK1_ILIM=0x5
BUCK1_VSET1=0x2d
BUCK1_VSET2=0x2d
BUCK1_OV_THR=0x3
BUCK1_UV_THR=0x3
BUCK1_GRP_SEL=0x1
BUCK1_RESET=0x0
BUCK1_FREQ_SEL=0x0
BUCK1_SEL_NEG_OCP_HYST=0x0
BUCK1_SEL_POS_OCP_HYST=0x1
BUCK1_SEL_ISENSE_SLOPE_COMPENSATION=0x2
BUCK1_SEL_VOUT_ADC_LEVEL=0x0
BUCK1_SEL_PHASE_SHEDD=0x0
BUCK1_SEL_PHASE_ADD=0x1
EN_LOAD_COMP_BLANK=0x1
BUCK1_SEL_OUTPUT_CAPS=0x2
BUCK1_SEL_RAMP=0x2
BUCK1_FREQ_8MHZ=0x0
BUCK1_EN_P_10M_BODY_DIODE=0x1
BUCK1_DOUBLE_PFM_PULSE=0x0
BUCK1_CHANGE_2MHZ_BELOW_0V5=0x0
BUCK1_EN_RADAR_MODE=0x0
swc_buck_hiz_1=0x0
BUCK2_EN=0x0
BUCK2_FPWM=0x1
BUCK2_VMON_EN=0x0
BUCK2_VSEL=0x0
BUCK2_PLDN=0x1
BUCK2_RV_SEL=0x0
BUCK2_SLEW_RATE=0x3
BUCK2_ILIM=0x5
BUCK2_VSET1=0x2d
BUCK2_VSET2=0x2d
BUCK2_OV_THR=0x3
BUCK2_UV_THR=0x3
BUCK2_GRP_SEL=0x1
BUCK2_RESET=0x0
BUCK2_FREQ_SEL=0x0
BUCK2_SEL_NEG_OCP_HYST=0x0
BUCK2_SEL_POS_OCP_HYST=0x1
BUCK2_SEL_ISENSE_SLOPE_COMPENSATION=0x2
BUCK2_SEL_VOUT_ADC_LEVEL=0x0
BUCK2_SEL_OUTPUT_CAPS=0x2
BUCK2_SEL_RAMP=0x2
BUCK2_FREQ_8MHZ=0x0
BUCK2_EN_P_10M_BODY_DIODE=0x1
BUCK2_DOUBLE_PFM_PULSE=0x0
BUCK2_CHANGE_2MHZ_BELOW_0V5=0x0
BUCK2_EN_RADAR_MODE=0x0
swc_buck_hiz_2=0x0
BUCK3_EN=0x0
BUCK3_FPWM=0x1
BUCK3_FPWM_MP=0x0
BUCK3_VMON_EN=0x0
BUCK3_VSEL=0x0
BUCK3_PLDN=0x1
BUCK3_RV_SEL=0x0
BUCK3_SLEW_RATE=0x0
BUCK3_ILIM=0x5
BUCK3_VSET1=0xfd
BUCK3_VSET2=0xfd
BUCK3_OV_THR=0x3
BUCK3_UV_THR=0x3
BUCK3_GRP_SEL=0x1
BUCK3_RESET=0x0
BUCK3_FREQ_SEL=0x0
BUCK3_SEL_NEG_OCP_HYST=0x0
BUCK3_SEL_POS_OCP_HYST=0x1
BUCK3_SEL_ISENSE_SLOPE_COMPENSATION=0x2
BUCK3_SEL_VOUT_ADC_LEVEL=0x0
BUCK3_SEL_PHASE_SHEDD=0x0
BUCK3_SEL_PHASE_ADD=0x1
BUCK3_SEL_OUTPUT_CAPS=0x2
BUCK3_SEL_RAMP=0x2
BUCK3_FREQ_8MHZ=0x0
BUCK3_EN_P_10M_BODY_DIODE=0x1
BUCK3_DOUBLE_PFM_PULSE=0x0
BUCK3_CHANGE_2MHZ_BELOW_0V5=0x0
BUCK3_EN_RADAR_MODE=0x0
swc_buck_hiz_3=0x0
BUCK4_EN=0x0
BUCK4_FPWM=0x0
BUCK4_VMON_EN=0x0
BUCK4_VSEL=0x0
BUCK4_PLDN=0x1
BUCK4_RV_SEL=0x0
BUCK4_SLEW_RATE=0x3
BUCK4_ILIM=0x5
BUCK4_VSET1=0x73
BUCK4_VSET2=0x73
BUCK4_OV_THR=0x4
BUCK4_UV_THR=0x4
BUCK4_GRP_SEL=0x1
BUCK4_RESET=0x0
BUCK4_FREQ_SEL=0x0
BUCK4_SEL_NEG_OCP_HYST=0x0
BUCK4_SEL_POS_OCP_HYST=0x1
BUCK4_SEL_ISENSE_SLOPE_COMPENSATION=0x2
BUCK4_SEL_VOUT_ADC_LEVEL=0x0
BUCK4_SEL_OUTPUT_CAPS=0x2
BUCK4_SEL_RAMP=0x2
BUCK4_FREQ_8MHZ=0x0
BUCK4_EN_P_10M_BODY_DIODE=0x1
BUCK4_DOUBLE_PFM_PULSE=0x0
BUCK4_CHANGE_2MHZ_BELOW_0V5=0x0
BUCK4_EN_RADAR_MODE=0x0
swc_buck_hiz_4=0x0
BUCK5_EN=0x0
BUCK5_FPWM=0x0
BUCK5_VMON_EN=0x0
BUCK5_VSEL=0x0
BUCK5_PLDN=0x1
BUCK5_RV_SEL=0x0
BUCK5_SLEW_RATE=0x3
BUCK5_ILIM=0x3
BUCK5_VSET1=0xb2
BUCK5_VSET2=0xb2
BUCK5_OV_THR=0x4
BUCK5_UV_THR=0x4
BUCK5_GRP_SEL=0x1
BUCK5_RESET=0x0
BUCK5_FREQ_SEL=0x0
BUCK5_SEL_NEG_OCP_HYST=0x0
BUCK5_SEL_POS_OCP_HYST=0x1
BUCK5_SEL_ISENSE_SLOPE_COMPENSATION=0x2
BUCK5_SEL_VOUT_ADC_LEVEL=0x0
BUCK5_SEL_OUTPUT_CAPS=0x2
BUCK5_SEL_RAMP=0x2
BUCK5_FREQ_8MHZ=0x0
BUCK5_EN_P_10M_BODY_DIODE=0x1
BUCK5_DOUBLE_PFM_PULSE=0x0
BUCK5_CHANGE_2MHZ_BELOW_0V5=0x0
BUCK5_EN_RADAR_MODE=0x0
swc_buck_hiz_5=0x0
SEL_LOOP_NEG_HYST=0x2
SEL_GATE_EARLY_SENSE=0x0
SEL_TRAD_NON_OVERLAP=0x0
SEL_FB_FILTER=0x3
SEL_RAMP_ARTIF=0x1
EN_SW_RT_SHORT_DETECTORS=0x0
EN_IAVE_LOOP_INJECTOR=0x0
EN_PLL_PROP_EXTEND=0x1
EN_SMART_OCP_BLANK=0x0
SEL_HS_DETECTOR=0x1
EN_LONG_PFM_EXIT_CNTR=0x1
EN_NEG_OCP=0x1
EN_POS_OCP=0x1
EN_PFM_LOAD=0x1
EN_DOT_MODE=0x1
LOOP_COEFF_I_BALANCE=0x1
SEL_ZERO_CROSS_FILTER_AVE=0x1
EN_AUTO_LOOP_COEFFS=0x1
LOOP_COEFF_FB_MSB=0x1
EN_LONG_ZERO_CROSS_FILTER=0x0
FORCE_SS_ADAPT=0x0
EN_PFM_PULSE_WAIT_LS_OCP=0x1
EN_SLOW_PLL_COEFFS=0x0
EN_SW_SHORT_DETECTORS=0x1
EN_FAST_PLL_0P7=0x1
EN_FAST_VOUT_INTEGRATION=0x1
EN_I_BALANCE_INTEGRATOR=0x1
DIS_PFM_WAITS_LS_DETECTOR=0x0
DIS_PFM_WAITS_HS_DETECTOR=0x0
DIS_DVS_WAIT_COMPARATORS=0x0
EN_CONSTANT_PLL_DVS_COEFF=0x0
EN_SLOW_PLL_0P3=0x1
EN_M_10M_TRAN_DETECTOR=0x1
EN_FAST_INTEGRATION_BYPASS_RAMP_RES=0x1
EN_LS_AFTER_HIZ=0x0
EN_PWM_LS_DETECTION=0x0
I_COEFF=0x1
BUCK_NEG_ILIM=0x1
EN_ADAPTIVE_SINGLE_SHOT=0x1
FIXED_SS_LENGTH=0x18
LONG_SINGLE_SHOT=0x1
LDO1_EN=0x0
LDO1_PLDN=0x1
LDO1_VMON_EN=0x0
LDO1_RV_SEL=0x0
LDO1_SLOW_RAMP=0x1
LDO1_VSET=0x3a
LDO1_BYPASS=0x0
LDO1_OV_THR=0x4
LDO1_UV_THR=0x4
LDO1_GRP_SEL=0x1
LDO1_RV_TIMEOUT=0xf
ldo1_en_short_cp=0x0
ldo1_dis_short_prot=0x0
ldo1_dis_ilim=0x0
ldo1_dis_cp_leak_comp=0x0
ldo1_en_cp_low_sr=0x0
ldo1_dis_ov_pldn=0x0
vbg_filt_config=0x0
LDO2_EN=0x0
LDO2_PLDN=0x0
LDO2_VMON_EN=0x0
LDO2_RV_SEL=0x0
LDO2_SLOW_RAMP=0x1
LDO2_VSET=0x1c
LDO2_BYPASS=0x0
LDO2_OV_THR=0x4
LDO2_UV_THR=0x4
LDO2_GRP_SEL=0x3
LDO2_RV_TIMEOUT=0xf
ldo2_en_short_cp=0x0
ldo2_dis_short_prot=0x0
ldo2_dis_ilim=0x0
ldo2_dis_cp_leak_comp=0x0
ldo2_en_cp_low_sr=0x0
ldo2_dis_ov_pldn=0x0
LDO3_EN=0x0
LDO3_PLDN=0x1
LDO3_VMON_EN=0x0
LDO3_RV_SEL=0x0
LDO3_SLOW_RAMP=0x1
LDO3_VSET=0x9
LDO3_BYPASS=0x0
LDO3_OV_THR=0x4
LDO3_UV_THR=0x4
LDO3_GRP_SEL=0x1
LDO3_RV_TIMEOUT=0xf
ldo3_en_short_cp=0x0
ldo3_dis_short_prot=0x0
ldo3_dis_ilim=0x0
ldo3_dis_cp_leak_comp=0x0
ldo3_en_cp_low_sr=0x0
ldo3_dis_ov_pldn=0x0
LDO4_EN=0x0
LDO4_PLDN=0x1
LDO4_VMON_EN=0x0
LDO4_RV_SEL=0x0
LDO4_SLOW_RAMP=0x1
LDO4_VSET=0x38
LDO4_OV_THR=0x4
LDO4_UV_THR=0x4
LDO4_GRP_SEL=0x1
LDO4_RV_TIMEOUT=0xf
ldo4_sel_low_ilim=0x0
ldo4_filter_current=0x3
GPIO1_OD=0x0
GPIO1_DIR=0x0
GPIO1_SEL=0x1
GPIO1_PU_SEL=0x0
GPIO1_PU_PD_EN=0x0
GPIO1_DEGLITCH_EN=0x0
GPIO1_OUT=0x0
GPIO2_OD=0x0
GPIO2_DIR=0x0
GPIO2_SEL=0x2
GPIO2_PU_SEL=0x0
GPIO2_PU_PD_EN=0x0
GPIO2_DEGLITCH_EN=0x0
GPIO2_OUT=0x0
GPIO3_OD=0x1
GPIO3_DIR=0x0
GPIO3_SEL=0x5
GPIO3_PU_SEL=0x0
GPIO3_PU_PD_EN=0x1
GPIO3_DEGLITCH_EN=0x1
GPIO3_OUT=0x0
GPIO4_OD=0x0
GPIO4_DIR=0x1
GPIO4_SEL=0x0
GPIO4_PU_SEL=0x0
GPIO4_PU_PD_EN=0x0
GPIO4_DEGLITCH_EN=0x0
GPIO4_OUT=0x0
GPIO5_OD=0x1
GPIO5_DIR=0x0
GPIO5_SEL=0x0
GPIO5_PU_SEL=0x0
GPIO5_PU_PD_EN=0x1
GPIO5_DEGLITCH_EN=0x1
GPIO5_OUT=0x0
GPIO6_OD=0x0
GPIO6_DIR=0x0
GPIO6_SEL=0x0
GPIO6_PU_SEL=0x0
GPIO6_PU_PD_EN=0x1
GPIO6_DEGLITCH_EN=0x1
GPIO6_OUT=0x0
GPIO7_OD=0x1
GPIO7_DIR=0x0
GPIO7_SEL=0x1
GPIO7_PU_SEL=0x0
GPIO7_PU_PD_EN=0x1
GPIO7_DEGLITCH_EN=0x0
GPIO7_OUT=0x0
GPIO8_OD=0x1
GPIO8_DIR=0x0
GPIO8_SEL=0x3
GPIO8_PU_SEL=0x0
GPIO8_PU_PD_EN=0x1
GPIO8_DEGLITCH_EN=0x0
GPIO8_OUT=0x0
GPIO9_OD=0x1
GPIO9_DIR=0x0
GPIO9_SEL=0x0
GPIO9_PU_SEL=0x0
GPIO9_PU_PD_EN=0x1
GPIO9_DEGLITCH_EN=0x1
GPIO9_OUT=0x0
GPIO10_OD=0x1
GPIO10_DIR=0x0
GPIO10_SEL=0x0
GPIO10_PU_SEL=0x0
GPIO10_PU_PD_EN=0x1
GPIO10_DEGLITCH_EN=0x1
GPIO10_OUT=0x0
GPIO11_OD=0x1
GPIO11_DIR=0x0
GPIO11_SEL=0x0
GPIO11_PU_SEL=0x0
GPIO11_PU_PD_EN=0x1
GPIO11_DEGLITCH_EN=0x1
GPIO11_OUT=0x0
NPWRON_SEL=0x0
ENABLE_PU_SEL=0x0
ENABLE_PU_PD_EN=0x1
ENABLE_DEGLITCH_EN=0x1
ENABLE_POL=0x0
NRSTOUT_OD=0x1
I2C_SPI_SEL=0x0
I2C1_SPI_CRC_EN=0x0
I2C2_CRC_EN=0x0
I2C1_ID=0x48
I2C2_ID=0x12
SPMI_CRC_EN=0x1
SPMI_MASTER_SEL=0x1
SPMI_CLK_SEL=0x2
SPMI_SLAVE_PASSIVE=0x0
SPMI_IF_SEL=0x0
SPMI_RETRY_LIMIT=0x3
SPMI_SLAVE_ASR_HOLD=0x0
SPMI_WD_AUTO_BOOT=0x1
SPMI_EN=0x0
SPMI_WD_EN=0x0
SPMI_WAKEUP_EN=0x0
SPMI_WD_BOOT_INTERVAL=0x8
SPMI_WD_RUNTIME_INTERVAL=0x8
SPMI_WD_RESPONSE_TIMEOUT=0x8
SPMI_PFSM_RESPONSE_TIMEOUT=0x8
SPMI_WD_BOOT_BIST_TIMEOUT=0x8
SPMI_WD_RUNTIME_BIST_TIMEOUT=0x8
BOOT_DELAY=0x0
SPMI_SID=0x5
SPMI_MID=0x0
FORCE_CLK_GATE=0x0
INT_LDO_PD_FORCE=0x0
LDO1_PD_FORCE=0x0
LDO2_PD_FORCE=0x0
LDO3_PD_FORCE=0x0
LDO4_PD_FORCE=0x0
SPMI_SLAVE_CNT=0x1
MCU_RAIL_TRIG=0x1
SOC_RAIL_TRIG=0x3
OTHER_RAIL_TRIG=0x2
SEVERE_ERR_TRIG=0x0
MODERATE_ERR_TRIG=0x1
GPIO1_FSM_MASK=0x1
GPIO1_FSM_MASK_POL=0x0
GPIO2_FSM_MASK=0x1
GPIO2_FSM_MASK_POL=0x0
GPIO3_FSM_MASK=0x1
GPIO3_FSM_MASK_POL=0x0
GPIO4_FSM_MASK=0x1
GPIO4_FSM_MASK_POL=0x0
GPIO5_FSM_MASK=0x0
GPIO5_FSM_MASK_POL=0x0
GPIO6_FSM_MASK=0x0
GPIO6_FSM_MASK_POL=0x0
GPIO7_FSM_MASK=0x1
GPIO7_FSM_MASK_POL=0x0
GPIO8_FSM_MASK=0x1
GPIO8_FSM_MASK_POL=0x0
GPIO9_FSM_MASK=0x0
GPIO9_FSM_MASK_POL=0x0
GPIO10_FSM_MASK=0x0
GPIO10_FSM_MASK_POL=0x0
GPIO11_FSM_MASK=0x0
GPIO11_FSM_MASK_POL=0x0
GPIO1_FALL_MASK=0x1
GPIO2_FALL_MASK=0x1
GPIO3_FALL_MASK=0x1
GPIO4_FALL_MASK=0x1
GPIO5_FALL_MASK=0x1
GPIO6_FALL_MASK=0x1
GPIO7_FALL_MASK=0x1
GPIO8_FALL_MASK=0x1
GPIO1_RISE_MASK=0x1
GPIO2_RISE_MASK=0x1
GPIO3_RISE_MASK=0x1
GPIO4_RISE_MASK=0x1
GPIO5_RISE_MASK=0x1
GPIO6_RISE_MASK=0x1
GPIO7_RISE_MASK=0x1
GPIO8_RISE_MASK=0x1
GPIO9_FALL_MASK=0x1
GPIO9_RISE_MASK=0x1
GPIO10_FALL_MASK=0x1
GPIO11_FALL_MASK=0x1
GPIO10_RISE_MASK=0x1
GPIO11_RISE_MASK=0x1
BUCK1_ILIM_MASK=0x0
BUCK1_OV_MASK=0x0
BUCK1_UV_MASK=0x0
BUCK2_ILIM_MASK=0x0
BUCK2_OV_MASK=0x0
BUCK2_UV_MASK=0x0
BUCK3_ILIM_MASK=0x0
BUCK3_OV_MASK=0x0
BUCK3_UV_MASK=0x0
BUCK4_OV_MASK=0x0
BUCK4_UV_MASK=0x0
BUCK4_ILIM_MASK=0x0
BUCK5_ILIM_MASK=0x0
BUCK5_OV_MASK=0x0
BUCK5_UV_MASK=0x0
LDO1_OV_MASK=0x0
LDO1_UV_MASK=0x0
LDO2_OV_MASK=0x0
LDO2_UV_MASK=0x0
LDO1_ILIM_MASK=0x0
LDO2_ILIM_MASK=0x0
LDO3_OV_MASK=0x0
LDO3_UV_MASK=0x0
LDO4_OV_MASK=0x0
LDO4_UV_MASK=0x0
LDO3_ILIM_MASK=0x0
LDO4_ILIM_MASK=0x0
VCCA_OV_MASK=0x0
VCCA_UV_MASK=0x0
NPWRON_START_MASK=0x1
ENABLE_MASK=0x0
FSD_MASK=0x1
SOFT_REBOOT_MASK=0x0
TWARN_MASK=0x0
BIST_PASS_MASK=0x0
EXT_CLK_MASK=0x1
BIST_FAIL_MASK=0x0
REG_CRC_ERR_MASK=0x0
SPMI_ERR_MASK=0x1
NPWRON_LONG_MASK=0x1
NINT_READBACK_MASK=0x0
NRSTOUT_READBACK_MASK=0x0
IMM_SHUTDOWN_MASK=0x0
MCU_PWR_ERR_MASK=0x0
SOC_PWR_ERR_MASK=0x0
ORD_SHUTDOWN_MASK=0x0
COMM_FRM_ERR_MASK=0x1
COMM_CRC_ERR_MASK=0x0
COMM_ADR_ERR_MASK=0x0
I2C2_CRC_ERR_MASK=0x0
I2C2_ADR_ERR_MASK=0x0
EN_DRV_READBACK_MASK=0x0
NRSTOUT_SOC_READBACK_MASK=0x1
ESM_SOC_PIN_MASK=0x1
ESM_SOC_RST_MASK=0x1
ESM_SOC_FAIL_MASK=0x1
ESM_MCU_PIN_MASK=0x0
ESM_MCU_RST_MASK=0x0
ESM_MCU_FAIL_MASK=0x0
PGOOD_SEL_BUCK1=0x1
PGOOD_SEL_BUCK2=0x1
PGOOD_SEL_BUCK3=0x1
PGOOD_SEL_BUCK4=0x1
PGOOD_SEL_BUCK5=0x1
PGOOD_SEL_LDO1=0x1
PGOOD_SEL_LDO2=0x1
PGOOD_SEL_LDO3=0x1
PGOOD_SEL_LDO4=0x1
PGOOD_SEL_VCCA=0x1
PGOOD_SEL_TDIE_WARN=0x1
PGOOD_SEL_NRSTOUT=0x1
PGOOD_SEL_NRSTOUT_SOC=0x0
PGOOD_POL=0x0
PGOOD_WINDOW=0x1
SS_EN=0x0
SS_DEPTH=0x0
SS_MODE=0x1
SS_PARAM1=0x7
SS_PARAM2=0xc
XTAL_EN=0x0
LP_STANDBY_SEL=0x0
STARTUP_DEST=0x3
XTAL_SEL=0x0
RTC_SPARE_0=0x0
RTC_SPARE_1=0x0
RTC_SPARE_2=0x0
RTC_SPARE_3=0x0
PFSM_DELAY1=0x0
PFSM_DELAY2=0x0
PFSM_DELAY3=0x0
PFSM_DELAY4=0x0
EXT_CLK_FREQ=0x0
TWARN_LEVEL=0x1
I2C1_HS=0x0
I2C2_HS=0x0
EN_ILIM_FSM_CTRL=0x0
NSLEEP1_MASK=0x1
NSLEEP2_MASK=0x0
TSD_ORD_LEVEL=0x1
BB_CHARGER_EN=0x0
BB_VEOC=0x0
BB_ICHR=0x0
PFSM_DELAY_STEP=0xb
USER_SPARE_1=0x0
USER_SPARE_2=0x0
USER_SPARE_3=0x0
USER_SPARE_4=0x0
refsys_bg_buf_hi_bw=0x0
refsys_sel_ibias=0x0
safety_speedup=0x1
safety_sel_ibias=0x0
safety_bg_buf_hi_bw=0x0
xtal_amp_reg_en=0x1
xtal_amp_reg_mode=0x1
xtal_comp_bias_lvl=0x0
xtal_bias_fine=0xa
EN_OVP=0x1
DIS_UVLO_OVP_RESET=0x0
DIS_TSD=0x0
PFSM_ERR_RESET_DIS=0x0
ABIST_ERROR_MASK=0x0
DIS_NRSTOUT_MCU_I2C_SPI_RESET=0x0
SLOW_AUTOZERO_SEL=0x0
EN_FIXED_DPLL_FREQ=0x0
SEL_RC_OSC=0x0
DISABLE_VM_NARROW_LIMITS=0x0
DISABLE_CHANGE_BG=0x0
DISABLE_USE_TRIMS=0x0
WD_EN_EE=0x1
PFSM_SEQ_MIN_TIME=0x1
SRAM_RELOAD_LIMIT=0x2
PFSM_PROXY_BRANCH_DIS=0x0
LPM_EN_DISABLES_VCCA_VMON=0x1
MAX_ILIM=0x5
FREQ_SEL_UNLOCK=0x0
REG_CRC_EN=0x0
EN_INITIALIZE_DPLL_RESTART=0x0
PFSM_ERR_MASK=0x0
FAST_VCCA_OVP=0x0
WD_RST_EN=0x1
WD_FAIL_TH=0x7
WD_RST_TH=0x7
FAST_BOOT_BIST=0x0
VSYS_DEAD_LOCK_EN=0x0
VMON_ABIST_EN=0x0
WD_EN=0x1
WD_LONGWIN=0xff
FAST_BIST=0x0
ESM_MCU_EN=0x0
ESM_SOC_EN=0x0
RECOV_CNT_THR=0xf
; instruction_set_version 2
; enable_optimization true
pfsm_start:
TRIG_SET DEST=immediateOff2Safe_pd ID=0 SEL=IMMEDIATE_SHUTDOWN TYPE=HIGH IMM=1 EXT=0
TRIG_SET DEST=orderlyOff2safe ID=1 SEL=ORDERLY_SHUTDOWN TYPE=HIGH IMM=1 EXT=0
TRIG_SET DEST=enterLPstandby ID=2 SEL=1 TYPE=HIGH IMM=0 EXT=0
TRIG_SET DEST=orderlyOff ID=3 SEL=FORCE_STANDBY TYPE=HIGH IMM=0 EXT=0
TRIG_SET DEST=warmReset ID=4 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 REENTRANT=1
TRIG_SET DEST=warmReset ID=5 SEL=ESM_MCU_ERROR TYPE=RISE IMM=0 EXT=0 REENTRANT=1
TRIG_SET DEST=RUNTIME_BIST ID=6 SEL=I2C_1 TYPE=RISE IMM=0 EXT=1 REENTRANT=1
TRIG_SET DEST=eni2cCRC ID=7 SEL=I2C_2 TYPE=RISE IMM=0 EXT=0 REENTRANT=1
TRIG_SET DEST=any2active ID=8 SEL=SU_ACTIVE TYPE=HIGH IMM=0 EXT=0
TRIG_SET DEST=any2active ID=9 SEL=WKUP1 TYPE=HIGH IMM=0 EXT=0
TRIG_SET DEST=orderlyOff ID=10 SEL=I2C_0 TYPE=HIGH IMM=0 EXT=0
TRIG_SET DEST=any2ota ID=11 SEL=I2C_3 TYPE=HIGH IMM=0 EXT=0
TRIG_SET DEST=waitForEnableSeq ID=12 SEL=FORCE_STANDBY TYPE=LOW IMM=0 EXT=0
TRIG_SET DEST=warmReset ID=13 SEL=MCU_POWER_ERROR TYPE=HIGH IMM=0 EXT=0
TRIG_SET DEST=ENVPP ID=14 SEL=GPIO9 TYPE=RISE IMM=0 EXT=0 REENTRANT=1
TRIG_SET DEST=DISVPP ID=15 SEL=GPIO9 TYPE=FALL IMM=0 EXT=0 REENTRANT=1
TRIG_SET DEST=SD_1V8 ID=16 SEL=GPIO5 TYPE=FALL IMM=0 EXT=0 REENTRANT=1
TRIG_SET DEST=SD_3V3 ID=17 SEL=GPIO5 TYPE=RISE IMM=0 EXT=0 REENTRANT=1
TRIG_SET DEST=RST_SDCARD ID=18 SEL=GPIO11 TYPE=FALL IMM=0 EXT=0 REENTRANT=1
TRIG_SET DEST=EN_SDCARD ID=19 SEL=GPIO11 TYPE=HIGH IMM=0 EXT=0 REENTRANT=1
TRIG_SET DEST=any2active ID=20 SEL=A TYPE=HIGH IMM=0 EXT=0
TRIG_SET DEST=any2_s2r ID=21 SEL=D TYPE=HIGH IMM=0 EXT=0
TRIG_SET DEST=SAFE_RECOVERY ID=22 SEL=1 TYPE=HIGH IMM=1 EXT=1
TRIG_MASK 0xFFFEFFC
END
any2active:
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x08 MASK=0xF3
REG_WRITE_MASK_IMM ADDR=0x3D DATA=0x08 MASK=0xF7
DELAY_IMM 10ms
REG_WRITE_VCTRL_IMM REGULATOR=BUCK3 VCTRL=0x10 MASK=0x6F DELAY_MODE=ALWAYS DELAY=0us
WAIT COND=GPIO10 TYPE=HIGH TIMEOUT=0us DEST=to_LPDDR4
REG_WRITE_VOUT_IMM REGULATOR=BUCK4 SEL=0 VOUT=1.2V DELAY=0us
to_LPDDR4:
WAIT COND=GPIO6 TYPE=HIGH TIMEOUT=0us DEST=vcore0V75_act
REG_WRITE_VOUT_IMM REGULATOR=BUCK1 SEL=0 VOUT=0.85V DELAY=0us
JUMP vcore_set_act
vcore0V75_act:
REG_WRITE_VOUT_IMM REGULATOR=BUCK1 SEL=0 VOUT=0.75V DELAY=0us
vcore_set_act:
REG_WRITE_VCTRL_IMM REGULATOR=BUCK5 VCTRL=0x11 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=LDO4 VCTRL=0x11 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK4 VCTRL=0x11 MASK=0x6E DELAY_MODE=ALWAYS DELAY=600us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK1 VCTRL=0x11 MASK=0x6E DELAY_MODE=ALWAYS DELAY=300us
REG_WRITE_VCTRL_IMM REGULATOR=LDO3 VCTRL=0x11 MASK=0x6E DELAY_MODE=ALWAYS DELAY=600us
DELAY_IMM 11000us
REG_WRITE_MASK_IMM ADDR=0x082 DATA=0x00 MASK=0xF7
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x01 MASK=0xFE
REG_WRITE_MASK_IMM ADDR=0x065 DATA=0x02 MASK=0xFD
TRIG_MASK 0xFC01004
END
orderlyOff:
REG_WRITE_MASK_IMM ADDR=0x082 DATA=0x08 MASK=0xF7
REG_WRITE_VCTRL_IMM REGULATOR=LDO2 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
DELAY_IMM 200us
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x00 MASK=0xFE
REG_WRITE_VCTRL_IMM REGULATOR=BUCK3 VCTRL=0x00 MASK=0x6F DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=LDO3 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=200us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK4 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=200us
DELAY_IMM 10ms
REG_WRITE_VCTRL_IMM REGULATOR=LDO4 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK5 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK1 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=1000us
REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=600us
DELAY_IMM 10ms
DELAY_IMM 1ms
REG_WRITE_MASK_IMM ADDR=0x3D DATA=0x00 MASK=0xF7
SET_DELAY 409.6us
DELAY_IMM 100ms
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF
REG_WRITE_MASK_IMM ADDR=0x2B DATA=0x00 MASK=0xFE
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xFB
REG_WRITE_MASK_IMM ADDR=0x081 DATA=0x04 MASK=0xE3
TRIG_MASK 0xFFFFCF4
WAIT COND=LP_STANDBY_SEL TYPE=HIGH TIMEOUT=0us DEST=stayinstandby
TRIG_MASK 0xFFFFFFB
stayinstandby:
SET_DELAY 102.4us
END
orderlyOff2safe:
REG_WRITE_MASK_IMM ADDR=0x082 DATA=0x08 MASK=0xF7
REG_WRITE_VCTRL_IMM REGULATOR=LDO2 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
DELAY_IMM 200us
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x00 MASK=0xFE
REG_WRITE_VCTRL_IMM REGULATOR=BUCK3 VCTRL=0x00 MASK=0x6F DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=LDO3 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=200us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK4 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=200us
DELAY_IMM 10ms
REG_WRITE_VCTRL_IMM REGULATOR=LDO4 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK5 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK1 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=1000us
REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=600us
DELAY_IMM 10ms
DELAY_IMM 1ms
REG_WRITE_MASK_IMM ADDR=0x3D DATA=0x00 MASK=0xF7
SET_DELAY 409.6us
DELAY_IMM 100ms
REG_WRITE_MASK_IMM ADDR=0x087 DATA=0x1F MASK=0xE0
SET_DELAY 102.4us
TRIG_MASK 0xFBFFFFF
END
immediateOff2Safe_pd:
REG_WRITE_MASK_IMM ADDR=0x082 DATA=0x08 MASK=0xF7
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x00 MASK=0xFE
REG_WRITE_MASK_IMM ADDR=0x087 DATA=0x1F MASK=0xE0
REG_WRITE_VCTRL_IMM REGULATOR=BUCK3 VCTRL=0x00 MASK=0x6F DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK1 VCTRL=0x20 MASK=0x4E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK4 VCTRL=0x20 MASK=0x4E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK5 VCTRL=0x20 MASK=0x4E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x20 MASK=0x0E DELAY_MODE=MATCH_EN DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=LDO2 VCTRL=0x20 MASK=0x0E DELAY_MODE=MATCH_EN DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=LDO3 VCTRL=0x20 MASK=0x0E DELAY_MODE=MATCH_EN DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=LDO4 VCTRL=0x20 MASK=0x0E DELAY_MODE=MATCH_EN DELAY=0us
REG_WRITE_MASK_IMM ADDR=0x3D DATA=0x00 MASK=0xF7
SET_DELAY 3276.8us
DELAY_IMM 500ms
SET_DELAY 102.4us
TRIG_MASK 0xFBFFFFF
END
warmReset:
REG_WRITE_MASK_IMM ADDR=0x082 DATA=0x08 MASK=0xF7
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x00 MASK=0xFE
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC
REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=1.8V DELAY=0us BYPASS=0
WAIT COND=GPIO6 TYPE=HIGH TIMEOUT=0us DEST=vcore0V75_rst
REG_WRITE_VOUT_IMM REGULATOR=BUCK1 SEL=0 VOUT=0.85V DELAY=0us
JUMP vcore_set_rst
vcore0V75_rst:
REG_WRITE_VOUT_IMM REGULATOR=BUCK1 SEL=0 VOUT=0.75V DELAY=0us
vcore_set_rst:
REG_WRITE_VOUT_IMM REGULATOR=BUCK5 SEL=0 VOUT=1.8V DELAY=0us
REG_WRITE_VOUT_IMM REGULATOR=BUCK3 SEL=0 VOUT=3.3V DELAY=0us
WAIT COND=GPIO10 TYPE=HIGH TIMEOUT=0us DEST=LPDDR4
REG_WRITE_VOUT_IMM REGULATOR=BUCK4 SEL=0 VOUT=1.2V DELAY=0us
JUMP DDR4
LPDDR4:
REG_WRITE_VOUT_IMM REGULATOR=BUCK4 SEL=0 VOUT=1.1V DELAY=0us
DDR4:
REG_WRITE_VOUT_IMM REGULATOR=LDO3 SEL=0 VOUT=0.85V DELAY=0us BYPASS=0
REG_WRITE_VOUT_IMM REGULATOR=LDO4 SEL=0 VOUT=1.8V DELAY=0us BYPASS=0
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB
REG_WRITE_MASK_IMM ADDR=0x0A5 DATA=0x01 MASK=0xFE
DELAY_IMM 10ms
DELAY_IMM 2ms
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x00 MASK=0xFC
DELAY_IMM 110us
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x01 MASK=0xFE
REG_WRITE_MASK_IMM ADDR=0x082 DATA=0x00 MASK=0xF7
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x08 MASK=0xF3
TRIG_MASK 0xFC01004
END
enterLPstandby:
REG_WRITE_MASK_IMM ADDR=0x021 DATA=0x01 MASK=0xFE
TRIG_MASK 0xFFFFFFF
END
eni2cCRC:
REG_WRITE_MASK_IMM ADDR=0x054 DATA=0x04 MASK=0xFB
REG_WRITE_IMM ADDR=0x0a2 DATA=0x98
REG_WRITE_IMM ADDR=0x0a2 DATA=0xB8
REG_WRITE_IMM ADDR=0x0a2 DATA=0x13
REG_WRITE_IMM ADDR=0x0a2 DATA=0x7D
REG_WRITE_MASK_IMM ADDR=0x11A DATA=0x06 MASK=0xF9
REG_WRITE_MASK_IMM ADDR=0x0EF DATA=0x02 MASK=0xFD
DELAY_IMM 2000us
REG_WRITE_MASK_IMM ADDR=0x054 DATA=0x00 MASK=0xFB
REG_WRITE_IMM ADDR=0x0a2 DATA=0x00
TRIG_MASK 0xFC01004
END
any2ota:
REG_WRITE_MASK_IMM ADDR=0x0C3 DATA=0x00 MASK=0x7F
TRIG_MASK 0xFC01004
END
waitForEnableSeq:
REG_WRITE_MASK_IMM ADDR=0xC3 DATA=0x80 MASK=0x7F
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x08 MASK=0xF3
TRIG_MASK 0xFFFFEFC
END
ENVPP:
REG_WRITE_VCTRL_IMM REGULATOR=LDO2 VCTRL=0x11 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
DELAY_IMM 2ms
TRIG_MASK 0xFC01004
END
DISVPP:
REG_WRITE_VCTRL_IMM REGULATOR=LDO2 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
TRIG_MASK 0xFC01004
END
SD_1V8:
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC
REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=1.8V DELAY=0us BYPASS=0
DELAY_IMM 10ms
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x00 MASK=0xFC
TRIG_MASK 0xFC01004
END
SD_3V3:
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC
REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=3.3V DELAY=0us BYPASS=1
DELAY_IMM 2ms
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x00 MASK=0xFC
TRIG_MASK 0xFC01004
END
any2_s2r:
REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x80 MASK=0x7F
REG_WRITE_MASK_IMM ADDR=0x082 DATA=0x08 MASK=0xF7
REG_WRITE_VCTRL_IMM REGULATOR=LDO2 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
DELAY_IMM 200us
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x00 MASK=0xFE
REG_WRITE_VCTRL_IMM REGULATOR=BUCK3 VCTRL=0x00 MASK=0x6F DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=LDO3 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=200us
DELAY_IMM 10ms
REG_WRITE_VCTRL_IMM REGULATOR=LDO4 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
REG_WRITE_VCTRL_IMM REGULATOR=BUCK1 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=1000us
REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=600us
DELAY_IMM 10ms
REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x00 MASK=0x7F
SET_DELAY 409.6us
DELAY_IMM 100ms
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF
REG_WRITE_MASK_IMM ADDR=0x2B DATA=0x00 MASK=0xFE
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB
REG_WRITE_MASK_IMM ADDR=0x081 DATA=0x04 MASK=0xE3
SET_DELAY 102.4us
TRIG_MASK 0xFCFFFF4
END
RST_SDCARD:
REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x00 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
DELAY_IMM 1ms
TRIG_MASK 0xFC01004
END
EN_SDCARD:
REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=3.3V DELAY=0us BYPASS=0
DELAY_IMM 1ms
REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x11 MASK=0x6E DELAY_MODE=ALWAYS DELAY=0us
DELAY_IMM 1ms
TRIG_MASK 0xFC01004
END

0 Kallikuppa Sreenivasa over 1 year ago in reply to Vinay S

TI__Guru**** 188979 points

Hello Vinay,

Thank you.

Seems like you have the PMIC in LDO mode and trying to change the supply voltage value between 3.3V and 1.8V. I don't know if this if fine, may be the PMIC team could answer.

I marked the values for 3.3V and 1.8V from the data sheet.

Can you try setting the value equivalent to 1.8V..

Regard,

Sreenivasa

0 Vinay S over 1 year ago in reply to Kallikuppa Sreenivasa

Intellectual 365 points

Hello Sreenivasa,

Thank you for the quick reply.

We are not able to set the value equivalent to 1.8V.

0x38 is the value for 1.8V and 0x74 is the value for 3.3V

If 1.8V is set manually using i2c commands in either u-boot or kernel PMIC warm reset occurs resulting in board reset.

Also request you to forward the query to PMIC team.

0 Kallikuppa Sreenivasa over 1 year ago in reply to Vinay S

TI__Guru**** 188979 points

Hello Vinay,

Thank you.

Looks like the values match the LDO4 table

I will reassign to the PMIC team to support.

Regards,

Sreenivasa

0 Vinay S over 1 year ago in reply to Kallikuppa Sreenivasa

Intellectual 365 points

Hello Sreenivasa,

The value 0x38 is a eight bit value written to the offset.

in that register only 1-6 bits are used for PMIC output voltage select so in 0x38 value will become 0x1C if only 1-6bits is taken hence it is same as table 8-4.

0 Kallikuppa Sreenivasa over 1 year ago in reply to Vinay S

TI__Guru**** 188979 points

Hello Vinay,

Thank you for clarifying.

Regards,

Sreenivasa

0 Nicholas McNamara over 1 year ago in reply to Vinay S

TI__Mastermind 20257 points

Hello Vinay,

I have some preliminary questions:

What part number is the PMIC on your board?

It looks like TPS65931211, correct?

Did you do any custom programming boot up programming to the PMIC?

0 Kallikuppa Sreenivasa over 1 year ago in reply to Nicholas McNamara

TI__Guru**** 188979 points

Hello Nicholas McNamara

In the interest of time i am answering for Vinay - please scroll up and read the seventh message from the bottom that has the custom OTP attached.

Refer summary below

In our board design we have changed the PMIC input voltage to 5V hence disabled bypass mode for the LDO's and linear regulator mode is enabled.

We notice that in EVK when voltage switching is disabled bypass mode is enabled and after switching voltage to 1.8V bypass mode will be disabled and voltage changes to 1.8V.

Regards,

Sreenivasa

0 Vinay S over 1 year ago in reply to Nicholas McNamara

Intellectual 365 points

Hello Nicholas McNamara,

I would like to add one more observation

In evm board we can modify the 0x23 offset under i2c in uboot and change the voltage from 1.8v to 3.3v based on table 8-4 in datasheet

but in our custom board the voltage value does not update even after writing to i2c registers and board resets when voltage is set to 3V and below

We are not sure what is causing this issue.

0 Nicholas McNamara over 1 year ago in reply to Vinay S

TI__Mastermind 20257 points

Hello Vinay & Kallikuppa,

comparing the differences between the OTP given in the thread versus what we have on file.

I do see that you have changed in the static configuration (everything before line 578), this does change the boot up to not be in bypass.

On lines [782:769], There is the BYPASS on 771, is 0, meaning that we're in LDO mode.

ON 778, the BYPASS=1, please change this BYPASS=0 so it can be used in LDO mode

SD_1V8:
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC
REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=1.8V DELAY=0us BYPASS=0
DELAY_IMM 10ms
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x00 MASK=0xFC
TRIG_MASK 0xFC01004
END
SD_3V3:
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC
REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=3.3V DELAY=0us BYPASS=1
DELAY_IMM 2ms
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x00 MASK=0xFC
TRIG_MASK 0xFC01004
END

What appears to be happening is that GPIO5 is held high for the default 3V3 on the SD_3V3, which according to the above should be acting as a load switch with a 3V3 input. Now that the input is 5V it fails and a warm reset occurs.

Please change this and let me know if that solves your issues.

Best Regards,

Nicholas.

0 Nicholas McNamara over 1 year ago in reply to Nicholas McNamara

TI__Mastermind 20257 points

My apologies on this,

I should say make these changes in the assembly and flash it to the PMIC, as it stands these are PFSM commands will keep expecting this behavior until it is flash.

BR,

Nicholas

0 Vinay S over 1 year ago in reply to Nicholas McNamara

Intellectual 365 points

Hi Nicholas McNamara,

We did the changes in recommended in the thread but it does not solve the issue.

Is there any other changes required if PMIC input voltage is 5V?

0 Nicholas McNamara over 1 year ago in reply to Vinay S

TI__Mastermind 20257 points

Hello Vinay,

please allow some time to look over the issue.

Vinay S said:
Is there any other changes required if PMIC input voltage is 5V?

See the above, what is for certain is that changing the 5V has changed the load switch behavior to LDO mode hand off for LDO12.

BR,

Nicholas

0 Vinay S over 1 year ago in reply to Nicholas McNamara

Intellectual 365 points

Hi Nicholas,

Any update on the issue.

0 Vinay S over 1 year ago in reply to Nicholas McNamara

Intellectual 365 points

Hi Nicholas,

Waiting for your reply on the issue.

Regards,
Vinay S

0 Nicholas McNamara over 1 year ago in reply to Vinay S

TI__Mastermind 20257 points

Hello Vinay,

could you update me, I'm looking over the thread again and it looks like you've been changing the settings in uboot as well?

Because it seems like you are making system changes, was the 5V change from the TI team or your changes?

Could you share schematic, registers 0x5A to 0x6C registers when there's a failure, it would help me conclude a possible solution.

BR,

Nicholas

0 Vinay S over 1 year ago in reply to Nicholas McNamara

Intellectual 365 points

Hi Nicholas,

Regarding the schematics rohith has already shared the section in below thread kindly refer the same.

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1262992/tps6593-q1-using-npwron-enable-pin-as-power-on-off-button?ReplyFilter=Answers&ReplySortBy=Answers&ReplySortOrder=Descending

Below are the register information

i2cdump -f -y 1 0x48
No size specified (using byte-data access)
     0 1 2 3 4 5 6 7 8 9 a b c d e f    0123456789abcdef
00: 00 9a 11 03 33 2b 23 2b 32 28 31 2b 31 1b 2d 2d    .???3+#+2(1+1?--
10: 2d 2d fd fd 73 73 b2 b2 1b 1b 1b 24 24 33 03 33    --??ss?????$$3?3
20: 33 00 00 74 38 12 38 24 24 24 24 20 7f 00 00 00    3..t8?8$$$$ ?...
30: 00 20 40 ba 01 1a 18 2a 6a 1a 1a 1a 19 08 00 dc    . @????*j?????.?
40: 0c 55 75 01 2d 01 55 50 00 00 00 00 00 00 00 ff    ?Uu?-?UP........
50: ff 3f 11 02 30 00 00 01 08 07 00 00 00 00 00 00    .???0..???......
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 02 00 00 00 00 55 01 55 99 00 43 00 00    ...?....U?U?.C..
80: 00 09 02 00 0f 00 03 00 00 00 00 0b ff ff 00 00    .??.?.?....?....
90: 00 00 00 00 00 00 00 00 00 00 00 60 00 00 00 00    ...........`....
a0: 00 00 00 80 00 00 08 00 00 00 00 00 00 00 00 00    ...?..?.........
b0: 00 00 00 00 00 38 00 00 01 01 00 00 00 00 00 00    .....8..??......
c0: 00 00 41 e5 02 00 00 00 00 00 00 00 00 00 00 00    ..A??...........
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 99 79    ..............?y

0 Nicholas McNamara over 1 year ago in reply to Vinay S

TI__Mastermind 20257 points

Hello Vinay,

so to continue using the TPS65931211 you need to make some hardware changes. As the change to the 5V has led to issues, these are outlined in the User's guide for the TPS65931211 with the Sitara processor in section: 3.1.2 Using 5V Input Supply

(Link to guide here)

BR,

Nicholas

0 Vinay S over 1 year ago in reply to Nicholas McNamara

Intellectual 365 points

Hi Nicholas,

These changes are implemented in our board for supporting 5V input.

Is there any additional changes required HW wise or in the OTP program?

Regards,

Vinay

0 Nicholas McNamara over 1 year ago in reply to Vinay S

TI__Mastermind 20257 points

Hello Vinay,

looking back at the information regarding the revision (0x04) for your part number I have tried a similar setup in order to place the SD_CARD power rail into bypass mode in order to accommodate your changes and I was unable to do so without getting interrupts that cause the PMIC. If you apply 5V with the rev4 you should be getting full power failures whenever you attempt to power from 5V. Based upon your schematic you will get this issue.

Assuming that you're actually on the latest revision which can handle the input power (VCCA) to be 5V on revision (0x05), you can change the load switch functionality to LDO mode for the SD card as the schematic you have shows me that you do have PVIN_LDO12 tied to the VCCA (5V). There is a circle tying the net together with the input power. I have provided the assembly code below, this change is only for development purposes only.

TPS651211_rev5_5V_sdcard_no_bypass

BR,

Nicholas

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AM62A7: PMIC warm reset occurs when voltage switching is enabled.