TDA4VM: UB949 no show

zhouyz zhou

Part Number: TDA4VM
Other Parts Discussed in Thread: ALP

hi TI:

I use UB949, to convert HDMI to 2 lvds show ,but not ok, i configure :

uint8_t Ub949Ub948Config[][4] = {

{0x1a, 0x03, 0xda, 0x5},
{0x1a, 0x04, 0xa0, 0x5},
{0x1a, 0x06, 0x58, 0x5},
{0x1a, 0x07, 0x60, 0x5},
{0x1a, 0x08, 0x62, 0x5},
{0x1a, 0x0c, 0x05, 0x5},
{0x1a, 0x0d, 0x20, 0x5},

{0x1a, 0x16, 0x02, 0x5},
{0x1a, 0x20, 0x4b, 0x5},
{0x1a, 0x22, 0x25, 0x5},
{0x1a, 0x40, 0x14, 0x5},
{0x1a, 0x41, 0x5c, 0x5},
{0x1a, 0x50, 0x97, 0x5},
{0x1a, 0x51, 0xa1, 0x5},
{0x1a, 0x52, 0x1e, 0x5},
{0x1a, 0x54, 0x28, 0x5},

{0x1a, 0x5b, 0x03, 0x5},

};

over 2 years ago

0 Fadi Abdulhameed over 2 years ago

TI__Mastermind 33980 points

Hey Zhouyz,

What do you mean by not ok? You see Black screen ?

Can you send me your system configuration (block diagram) of how your system is connected.
What display timing are you using? Do you have the full timing spec and PCLK ?
So you're using the UB949 to UB948 and using dual OLDI output on 984?
Please send a full register dump of the Ser and Des at power-up.
Have you tried internal patgen testing from UB949 side does that work?

Regards,
Fadi A.

0 zhouyz zhou over 2 years ago in reply to Fadi Abdulhameed

Prodigy 80 points

yes no clk, I use UB948 UB949

0 Fadi Abdulhameed over 2 years ago in reply to zhouyz zhou

TI__Mastermind 33980 points

Hey Zhouyz,

We need more details to be able to debug this issue.

provide register dump of Ser and Des after system power-up
Do you have access to Analog LaunchPad software?
have you tried running patgen testing from Ser or Des to isolate the issue further? If not please do the following

Need to check whether the issue is timing or CLK issue. We have a few modes that you could run for additional debug. UB941AS supports multiple modes:

1- Internal - everything will be internally generated; HS, VS, DE, CLK and Video (if no issue is observed then the issue is likely coming from the video source)

2- Internal w/ext clk is HS, VS, DE and Video are generated internally but using External PCLK (if you see an issue in this mode, this point to an external CLK issue from the source)

3- External is HS, VS, DE and CLK are generated externally (if you see an issue in this mode, this point to an external CLK/timing issue from the source)

If you have ALP you could do this type of testing from the user-interface and select different timing sources with different resolutions and patterns.

If you don't have ALP ... I need your display timing and PCLK to generate a script for you.

Regards,
Fadi A.

0 zhouyz zhou over 2 years ago in reply to Fadi Abdulhameed

Prodigy 80 points

Thanks , I dont have ALP, my timing is：

prm->display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_DPI_HDMI;
prm->timings.width = 1280U;
prm->timings.height = 768U;
prm->timings.hFrontPorch = 110U;
prm->timings.hBackPorch = 220U;
prm->timings.hSyncLen = 40U;
prm->timings.vFrontPorch = 5U;
prm->timings.vBackPorch = 20U;
prm->timings.vSyncLen = 5U;
prm->timings.pixelClock = 74250000ULL;

0 zhouyz zhou over 2 years ago in reply to Fadi Abdulhameed

Prodigy 80 points

this clock only IN_CLK+ not IN_CLK- ， here need set register?

0 Fadi Abdulhameed over 2 years ago in reply to zhouyz zhou

TI__Mastermind 33980 points

Hey Zhouyz,

zhouyz zhou said:
prm->timings.width = 1280U;
prm->timings.height = 768U;

Are those your active horizontal and active vertical?

Which means your total horizonal = 1138?

and your total vertical = 798?

Please confirm.

Regards,
Fadi A.

0 zhouyz zhou over 2 years ago in reply to Fadi Abdulhameed

Prodigy 80 points

active horizontal and active vertica is 1280 768

0 Fadi Abdulhameed over 2 years ago in reply to zhouyz zhou

TI__Mastermind 33980 points

Hey Zhouyz,

I have the mode_sel straps set to the following:

DS90UB949:

IDx = 0x18 for I2C

Mode_Sel0 = #first mode

Mode_Sel1 = #first mode

DS90UB948:

IDx = 0x58 for I2C

Mode_Sel0 = #first mode

Mode_Sel1 = #first mode

Here is my bench setup.

1- Power-up Ser / Des

2- Video will work immediately after power-up if 949 is plugged into an HDMI source

3- If you want to access 948 registers you need to write 0xDA to register 0x3 on the 949 side to enable I2C passthrough.

4- run the scripts attached from the 949 side that are programmed with your timing - you can see now I'm using patgen and the resolution is as the one you provided. I have no issues on my setup

Here are the scripts that you need to run - Please report back the results:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/949_2D00_948-Scripts.7z

Script	949	948	Display output Result
941AS_1280_768_Script_Internal_Patgen_66.7Mhz	Reg 0xC = ? Reg 0x3 = ?	Reg 0x1C = ?	Black screen/ colorbar?
941AS_1280_768_Script_Internal_Patgen_100Mhz	Reg 0xC = ? Reg 0x3 = ?	Reg 0x1C = ?	Black screen/ colorbar?
941AS_1280_768_Script_Internal_timing_Ext_CLK	Reg 0xC = ? Reg 0x3 = ?	Reg 0x1C = ?	Black screen/ colorbar?
941AS_1280_768_Script_Ext_timing_Ext_CLK	Reg 0xC = ? Reg 0x3 = ?	Reg 0x1C = ?	Black screen/ colorbar?

Here are the expected registers values on 949 and 948 after power-up

Register	UB949	Description
0xC	0x3	Link detected
0x3	0xDA	I2C Passthrough

Register	UB948
0x1C	0x3B	Lock detected

Regards,
Fadi A.

0 zhouyz zhou over 2 years ago in reply to Fadi Abdulhameed

Prodigy 80 points

Fadi Abdulhameed Thanks , I try it.

0 zhouyz zhou over 2 years ago in reply to zhouyz zhou

Prodigy 80 points

[MCU2_0] 13.822748 s: DSS HDMI: Write Success for ClientAddr 0x1a RegAddr 0x3 Value 0xda !
[MCU2_0] 13.827748 s: DSS HDMI: Write Success for ClientAddr 0x1a RegAddr 0x54 Value 0x0 !
[MCU2_0] 13.832748 s: DSS HDMI: Write Success for ClientAddr 0x1a RegAddr 0x5b Value 0xa0 !
[MCU2_0] 13.837748 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0x3 Value 0xda !
[MCU2_0] 13.842748 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0x6 Value 0x70 !
[MCU2_0] 13.847748 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0x5b Value 0xa0 !
[MCU2_0] 13.852749 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0x5a Value 0x92 !
[MCU2_0] 13.857748 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0x5d Value 0x6 !
[MCU2_0] 13.862748 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0x5e Value 0x44 !
[MCU2_0] 13.867748 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0x5f Value 0x0 !
[MCU2_0] 13.872748 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0xf1 Value 0x55 !
[MCU2_0] 13.877748 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0xc Value 0x1 !
[MCU2_0] 13.882748 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0x4f Value 0x0 !

I try 0x03 ---> 0xda 0x5b ---> 0xa0(I use coax) but 0x5a is 0x92 no clk?

0 Fadi Abdulhameed over 2 years ago in reply to zhouyz zhou

TI__Mastermind 33980 points

Hey Zhouyz,

zhouyz zhou said:
[MCU2_0] 13.877748 s: DSS HDMI: Read Success for ClientAddr 0x1a RegAddr 0xc Value 0x1 !

Is this register 0xC read back value of 0x1 on the 949?

zhouyz zhou said:
I try 0x03 ---> 0xda 0x5b ---> 0xa0(I use coax) but 0x5a is 0x92 no clk?

0x5a = 0x92 means you either don't have CLK present at the input or you do have CLK but it's unstable from the video source. This is not an FPD-Link issue, please follow up with the HDMI source IC team to figure out why you're having issues on the HDMI CLK signal.

Have you tried running the scripts I gave you? The script labeled "941AS_1280_768_Script_Internal_Patgen_66.7Mhz" will use internal clock from our device to display the colorbar patgen, did that work?

Regards,
Fadi A.

0 zhouyz zhou over 2 years ago in reply to Fadi Abdulhameed

Prodigy 80 points

Thanks Fadi,

I set color bar to 948 is ok,

0 Fadi Abdulhameed over 2 years ago in reply to zhouyz zhou

TI__Mastermind 33980 points

Hey Zhouyz,

Ok so if colorbar script with internal timing works fine then this confirms the issues is from the HDMI source.

Regards,
Fadi A.

0 zhouyz zhou over 2 years ago in reply to Fadi Abdulhameed

Prodigy 80 points

Thanks Fadi:

I run script is ok, No HDMI source, beacuse no clk.

0 Fadi Abdulhameed over 2 years ago in reply to zhouyz zhou

TI__Mastermind 33980 points

Hey Zhouyz,

Thank for confirming I will go ahead and close this thread.

Regards,
Fadi A.

0 zhouyz zhou over 2 years ago in reply to Fadi Abdulhameed

Prodigy 80 points

Hi Fradi:

my UB949 ---> UB948 is ok, but I set HDMI clk 142M ,UB948 no show, I set 74.25M can show , why? and I want to show different resolution Image like UB941? you know how set UB949?

0 Fadi Abdulhameed over 2 years ago in reply to zhouyz zhou

TI__Mastermind 33980 points

Hey Zhougz,

I'm not sure I fully understand your question? Can you please describe what you are requesting in more detail please.

Regards,
Fadi A.

0 zhouyz zhou over 2 years ago in reply to Fadi Abdulhameed

Prodigy 80 points

I mean I use different camera combine a large image to use UB949 show different two port

0 Fadi Abdulhameed over 2 years ago in reply to zhouyz zhou

TI__Mastermind 33980 points

Hey Zhougz,

I will review and get back to you tomorrow.

Regards,
Fadi A.

0 Fadi Abdulhameed over 2 years ago in reply to Fadi Abdulhameed

TI__Mastermind 33980 points

Hey Zhougz,

Are you running single or dual FPD-Link channel? Please check if you're PCLK is higher than the supported BW.

Regards,
Fadi A.

0 zhouyz zhou over 2 years ago in reply to Fadi Abdulhameed

Prodigy 80 points

Thanks Fadi:

you mean I only use single channel pixel clk up 96Mz use two channel up 196Mhz . I now use 2 port and 142Mhz but not show , use 74Mhz is show but the image is not good.

0 Hamzeh Jaradat over 2 years ago in reply to zhouyz zhou

TI__Guru** 115020 points

Hello Zhouyz,

as Fadi OoO, can you please summarize the issue so that I can support you?

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TDA4VM: UB949 no show