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DRA726: Low Power operational modes for the DRA726x

Nesrine Harbaoui
Prodigy 20 points

Part Number: DRA726
Other Parts Discussed in Thread: TPS65917-Q1,

Hello all,

I'm currently working on a project implementing a DRA726x processor (DRA726APGABCQ1 to be exact), which is used along with TPS65917-Q1.

What are the low power modes for each one of the IC's (the DRA726 processor and TPS65917 PMIC) ? And how much current is drawn of them in these operational modes (preferably under 5 mA and if possible under 1 mA)?

If no operational mode is available under 5mA than what seems to be the closest operational mode to that range ?

Regards

  • 0
    TI__Expert 7535 points

    The DRA726x processor does not directly support very low power modes such as IO Retention but it can support a system level Suspend to RAM (S2R) low power mode. The DRA72x TRM section 3.1.2 describes the SoC specific power management techniques and the TPS65917 data sheet should be referenced for understanding the PMIC power states & dissipation (PMIC FAEs can be contacted to address specific questions). The TI DRA72x / TDA2Eco EVM has a power solution supports system S2R as an example but the actual S2R power performance has not been characterized. 

    To achieve 1-5mA (assuming this is battery Vin load), the majority of the processor would need to be powered down and only the 1st stage pre-regulator, PMIC & a few discrete power devices would remain energized to sustain the system in a low power mode (i.e. Suspend to RAM).  Obviously, achieving 1-5mA load at the battery Vin is challenging and will take detailed evaluation of fully system Power Delivery Network (PDN) by end product system engineers.

  • 0 in reply to Bill McCracken
    Prodigy 20 points

    Hey Bill, 

    Thank you for your respond, I really appreciate it.

    Since the DRA family can support the "Suspend to RAM" system state, can you please provide more details regarding this state and how to activate it (configure it).

    Thank you,