AM623: MMCSD0_CTRL_4_REG & PHY_CTRL_5_REG Register

Gibbs, we do not recommend changing these values. These values were selected based on detailed timing analysis of the AM62x device and the SDIO/SD Card standard using the trace delay limits defined in the Timing Conditions table. The recommended value applies the appropriate data to clock delay to be compliant with the SDIO/SD Card standard across the AM62x process, voltage, and temperature variations. Shifting the relationship to provide more hold margin will simply erode setup time margin.

Please explain why you feel this value needs to be adjusted to provide more hold margin.

Regards,
Paul

Hi, Paul

I agree with your opinion, but we have SDIO CLK/DATA hold time insufficient problems

Customer use mmc2 interface connect CC3300 in high speed mode (HS).

Follow these thread, we already make sure AM62x works in HS mode

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1321305/am623-is-it-possible-to-adjust-sdio-setup-time-hold-time-for-clk-data-line/5029033?tisearch=e2e-sitesearch&keymatch=%252520user%25253A533255#5029033

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1342895/am623-how-to-make-sure-mmc2-works-in-correct-sdio-speed-mode?tisearch=e2e-sitesearch&keymatch=%2525252520user%252525253A533255#

And we already know this chart is AM62x TX & CC3300 for RX, CC3300 is in RX mode.

Follow spec, hold time should be 2ns, but we measure it around < 0.8ns

I already run out of my idea, so that is way I start studying MMCSD0_SS_PHY_CTRL_4_REG

Gibbs

The host controller still appears to be configured such that it is changing data on the rising edge of clock. This peripheral was timing closed to perform High Speed data transfers with data changing on the falling edge of clock. You must change the controller to launch data on the falling edge of clock.

Regards,
Paul

Hi, Paul

Appreciate your reply.

To make sure I do not misunderstand your meaning.

Should we need to "change software" setting for "launching data on the falling edge of clock"?

I guess software change as below, but I am not very sure.

May you help us double check it?

Many Thanks

Gibbs

I will need to ask someone from the software team to tell you how to configure the host controller such that it changes data on the falling edge of clock. I seem to recall there is a bit in some host controller register named High Speed Enable. This bit should only be set when using a data transfer mode that requires data to change on the rising edge of clock. You can see which edge the data is expected to change by examining the figure following the respective Switching Characteristics section. For example, you can clearly see the data is expected to change on the falling edge of clock in the snapshot you inserted above taken from the High Speed Switching Characteristics section of the datasheet. Ignore the name of the bit and simply think of it as the bit that changes the data launch edge. If low, the data changes on the falling edge of clock. If high, data changes on the rising edge of clock.

Regards,
Paul

Paul & Bin

Thanks!

Lets me try and studying

Gibbs