Tool/software:
Hi AM69 Champ !
The model we are going to develop will use USB3.0 using serDer0 and SSD or M.2 using PCIE.
In the reference manual, REFCLK of PCI and usb3.0 is specified as 100MHz as above, and 100MHz is being input to SERDES0_REFCLK (AU8 / AU9) using CLOCK GENERATORS to EVM.
Is it possible to use the PCI CLK OUT using the PLL inside the CPU without using external CLOCK GENERATORS? Also, please let me know if there is anything in particular that I should pay attention to.
If I set MAIN_PLL2_HSDIV4_CLKOUT above, can I use PCI and USB without SERDES0_REFCLK input?
Is it possible to use PCIE_REFCLKx_x_OUT as CLK input of PCIE device without SERDES0_REFCLK input?
Please clarify the quation above. Thanks.
Regards, Jack
