DM8168: DDR3 Configuration

Alex Wong CS

Hi forum,

I have questions about the DDR3 device configuration in DM8168.
Target to build 2GByte total address space.

(1) To achieve this, is 8 x 2Gb devices the only config?
In this case, the connection can follow that of Netra EVM, Fig 8-14 in DS and Fig 7-9 in TRM.
Just the device is changed to Micron MT41J256M8HX.

(2) When study NETRA EVM, there are some resistor arrays in DDR data bus.
The bit mapping is different from a simple one. From the diagrams, I thought Byte[7]->DQ[7], Byte[6]->DQ[6], and so on.
Is there any special purpose to do so? Should I follow the same mapping as NETRA EVM?

(3) Any recommended material about routing and advice?

Thanks for your quick help and support.

Best regards,
Alex

over 14 years ago

0 MarcPyne over 14 years ago

TI__Mastermind 25055 points

Hello,

The datasheet shows the possible DDR3 configurations for this device (please do not refer to the TRM connection figures.) For the data pins, you can have a direct pin mapping, or data swizzling (i.e. Netra D0 pin goes to memory D2 pin) is a common practice and it is okay to rearrange the data bits within a byte. Just keep the entire bytes together and there will be no issue.

The EVM can be used as a reference, but the key is to very closely follow the DDR3 specifications in the DM8168 datasheet.

Regards,
Marc

0 Alex Wong CS over 14 years ago in reply to MarcPyne

Intellectual 340 points

Hi Marc,

Thanks, so I shall refer to DDR3 spec in DM8168 datasheet (SPRS614).

It is stated that max memory device capacity is 2Gbit, that means I need 8 devices to achieve 2GByte.

About the data swizzling, keeping the entire bytes => separation of byte as in Figure 8-14?

It can be swizzling within a byte to a device, but not across the bytes from the memory controller, right?

Regards,

Alex

0 MarcPyne over 14 years ago in reply to Alex Wong CS

TI__Mastermind 25055 points

Hi Alex,

That is correct, swizzling only within a byte.

Regards,
Marc

0 Alex Wong CS over 14 years ago in reply to MarcPyne

Intellectual 340 points

Hi Marc,

In DM8168, is it possible to achieve 2GByte total address space using x16 devices?

Thanks for your hint.

Regards,

Alex

0 MarcPyne over 14 years ago in reply to Alex Wong CS

TI__Mastermind 25055 points

Alex,

Yes, each EMIF can support up to 2 GB total address space. For DDR3 you can use 8-bit or 16-bit devices.

Regards,
Marc

0 Alex Wong CS over 14 years ago in reply to MarcPyne

Intellectual 340 points

Marc,

I'm a bit confused after reading your reply, would be glad if you can clarify the statements from datasheet.

(a) 2 GB Total Address Space

From your reply, this 2GByte address space limit is per each EMIF. This the whole IC can support up to 4GByte in total.

(b) Maximum memory device capacity: 2Gbit device

This applies for both x8 and x16, right?

From my understanding, this seems to be a total of EMIFs.

Each EMIF can support at most four devices (either four on a single side PCB, or two pairs in mirror mounting)

Thank you for your quick clarification.

Regards,

Alex

0 MarcPyne over 14 years ago in reply to Alex Wong CS

TI__Mastermind 25055 points

Alex,

Sorry for any confusion. The answer is Yes to all of your questions.

Regards,
Marc

0 MarcPyne over 14 years ago in reply to Alex Wong CS

TI__Mastermind 25055 points

Alex,

I misspoke in my answer to your first question - the total address space is 2GB, not per EMIF.

Regards,
Marc

0 Harish Naidu over 11 years ago in reply to MarcPyne

Prodigy 110 points

Dear MarcPyne,

We are using the DM8168 ti custom board and facing issue in the DDR3(MT41K256M16HA-125) read/write, DDR3 writes and reads up 8KB after that its overwrites.

We are configuring the DDR3 as per our data sheet and modified the gel gel file as per spreadsheet register xls sheet and getting the value as below:

#define EMIF_TIM1_DDR3_796 0x1779c9ee

#define EMIF_TIM2_DDR3_796 0x50d87ff4

#define EMIF_TIM3_DDR3_796 0x001f8cff

#define EMIF_SDREF_DDR3_796 0x10001844

#define EMIF_SDCFG_DDR3_796 0x6AA73B33

/* 32 bit ddr3, CL=11, 8 banks, CWL=8 10 bit column, 2 CS, */

#define EMIF_PHYCFG_DDR3_796 0x00100110 /* local odt = 3, read latency = 11 (max = 12, min=6) */

Please suggest us why DDR3 does not write after 8KB.

Thanks,

Harish N

0 Pavel Botev over 11 years ago in reply to Harish Naidu

TI__Guru**** 170625 points

Hi Harish,

At what DDR3 frequency you observe the read/write issue? Can you try with the lowest frequency supported by the DDR3, do you have the same issue?

Regards,
Pavel

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DM8168: DDR3 Configuration