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Original question:

AM625: Unexpected GPIO behavior when resuming from the Deep Sleep mode.

[FAQ] AM625: I/O leakage current

OLEKSIY KASYAN
Prodigy 70 points
Part Number: AM625

Tool/software:

Hi support team.

I'm working now on the product based on the AM62x processor.

When reading the datasheet I spotted some information that can affect my design.

Does the leakage current for the I/O pins really can go up to 10uA? In which condition.

Please help me understand.

How big leakage current for the I/O pin I should expect when the CPU is in the Reset state?

As an example lets take a GPMC0_CLK (P25) pin used as an Output. How big leakage current I should expect for this pin in a Reset state?

Thank you.

  • 0
    TI__Mastermind 18580 points

    Hello,

    Let me loop in the hardware team to comment.

  • 0 in reply to Anshu Madwesh
    TI__Guru 63145 points

    We only define one value for this parameter, and it is inclusive of all operating conditions.  We do not have additional data for specific operating conditions.

    Please explain how this is creating a problem for your product design to see if I can offer any suggestions.

  • 0 in reply to peaves
    Prodigy 70 points

    Hi Peaves

    We have a situation where the power to peripheral devices is controlled by the GPIO pins of the AM62 SoC. To ensure that these peripheral devices remain unpowered when the AM62 I/O pins are not driven (i.e., when the AM62x SoC is in Reset), we have placed 100k pull-down resistors on the respective pins, as illustrated in the image below.

    As I understand it, the I/O pins of the AM62x SoC are tri-stated when the SoC is in Reset, causing the Enable pin of the peripheral device to be pulled down, which in turn keeps the device unpowered.

    However, if the leakage current of the AM62x SoC can reach up to 10µA in a Reset state, this could cause a significant voltage drop across the 100k pull-down resistor. This voltage drop might be sufficient to turn on a MOSFET transistor, for example.

    Therefore, my questions are as follows:

    • Can the leakage current of the AM62x SoC actually reach 10µA, and under what conditions does this occur?
  • 0 in reply to OLEKSIY KASYAN
    TI__Guru 63145 points

    10uA is the limit for device pass/fall during final test, so there is a very small probability that you could get some devices that have up to 10uA of leakage. 

    You may need to reduce the resistance of the pull-down to ensure the attached device is not enabled by the IO leakage.

    Note: The more advanced process nodes have higher leakage due to the smaller transistors.

    Regards,
    Paul