Other Parts Discussed in Thread: AM6442, , SYSCONFIG
Tool/software:
Hi everybody,
I'm actually facing an issue trying to boot a Linux appimage from custom SBL. The SBL start correctly but when OP-TEE try to access HUK in A53 SPL I got the error :
E/TC:0 0 tee_otp_get_hw_unique_key:103 Could not get HUK, with error : ffff0001 (access_denied). I tried to debug by putting print in OP-TEE and it seems that the error is due to a mismatch of permission flags with TI_SCI_FLAG_RESP_GENERIC_ACK in the mailbox message comming from proxy thread.
Actually, I compile my SBL with MCU+SDK and generate my appimage with linuxAppimageGen.
I compile OP-TEE with the following command : make -j8 CROSS_COMPILE64="$CROSS_COMPILE_64" CROSS_COMPILE32="$CROSS_COMPILE_32" PLATFORM=k3 CFG_TEE_SUPP_LOG_LEVEL=4 CFG_TEE_CORE_DEBUG=y RPMB_EMU=0 CFG_ARM64_core=y CFG_REE_FS=y DEBUG=y CFG_TEE_CORE_LOG_LEVEL=4
And u-boot with : make ARCH=arm CROSS_COMPILE="$CROSS_COMPILE_64" -j8 BINMAN_INDIRS=/home/baptiste/Documents/Custom_linux_env/prebuilt-images BL31=/home/baptiste/Documents/Custom_linux_env/prebuilt-images/bl31.bin TEE=/home/baptiste/Documents/optee_os/out/arm-plat-k3/core/bl32.bin O=build/a53
and i put bl32.bin and u-boot-spl.bin from u-boot/build/a53/spl in the config.mak to compile appimage.
I try to boot the SBL from OSPI and directly from the SD card by replacing tiboo3.bin by my SBL but the result is the same.
My SD card contain one part with uboot.img. tispl.bin tiboot3.bin and my appimages and the rootfs in the second part (everything is working correctly when i use the original tiboot3.bin and boot fom sd card by bypassing the custom SBL)
I use the MCU+SDK with GP mode in devconfig to use hs-fs. I also tried to compile everything with HS but it change nothing.
Boot logs :
Starting SD Bootloader ... DMSC Firmware Version 9.1.6--v09.01.06 (Kool Koala) DMSC Firmware revision 0x9 DMSC ABI revision 3.1 Files read from sd card Multicore image parsing is OK ParseAndLoad 0 ParseAndLoad 1 ParseAndLoad 2 ParseAndLoad 3 ParseAndLoad 4 ParseAndLoad 5 Linux app image parsing is OK [BOOTLOADER_PROFILE] Boot Media : SD Card [BOOTLOADER_PROFILE] Boot Image Size : 989 KB [BOOTLOADER_PROFILE] Cores present : r5f0-0 r5f0-1 a530-0 [BOOTLOADER PROFILE] SYSFW init : 12177us [BOOTLOADER PROFILE] System_init : 30543us [BOOTLOADER PROFILE] Drivers_open : 115253us [BOOTLOADER PROFILE] Board_driversOpen : 2833us [BOOTLOADER PROFILE] Sciclient Get Version : 9913us [BOOTLOADER PROFILE] File read from SD card : 96051us [BOOTLOADER PROFILE] CPU load : 8907us [BOOTLOADER_PROFILE] SBL Total Time Taken : 358837us Image loading done, switching to application ... NOTICE: BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty NOTICE: BL31: Built : 16:09:05, Feb 9 2024 NOTICE: Upgrade Firmwares for Power off functionality ERROR: GTC is disabled! Timekeeping broken. Fix Bootloader ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader D/TC:0 plat_get_aslr_seed:112 Warning: no ASLR seed D/TC:0 add_phys_mem:750 VCORE_UNPG_RX_PA type TEE_RAM_RX 0x9e800000 size 0x00075000 D/TC:0 add_phys_mem:750 VCORE_UNPG_RW_PA type TEE_RAM_RW 0x9e875000 size 0x0018b000 D/TC:0 add_phys_mem:750 ta_base type TA_RAM 0x9ea00000 size 0x01200000 D/TC:0 add_phys_mem:750 SEC_PROXY_RT_BASE type IO_SEC 0x4a600000 size 0x00200000 D/TC:0 add_phys_mem:750 SEC_PROXY_SCFG_BASE type IO_SEC 0x4a400000 size 0x00200000 D/TC:0 merge_mmaps:703 Merging 0x4a600000..0x4a7fffff and 0x4a400000..0x4a5fffff D/TC:0 add_phys_mem:750 SEC_PROXY_DATA_BASE type IO_SEC 0x4d000000 size 0x00200000 D/TC:0 add_phys_mem:750 CONSOLE_UART_BASE type IO_NSEC 0x02800000 size 0x00200000 D/TC:0 add_phys_mem:750 GICD_BASE type IO_SEC 0x01800000 size 0x00200000 D/TC:0 add_phys_mem:750 GICC_BASE type IO_SEC 0x01800000 size 0x00200000 D/TC:0 merge_mmaps:703 Merging 0x1800000..0x19fffff and 0x1800000..0x19fffff D/TC:0 add_phys_mem:750 TEE_SHMEM_START type NSEC_SHM 0x9fc00000 size 0x00400000 D/TC:0 add_va_space:794 type RES_VASPACE size 0x00a00000 D/TC:0 add_va_space:794 type SHM_VASPACE size 0x02000000 D/TC:0 dump_mmap_table:921 type NSEC_SHM va 0x99800000..0x99bfffff pa 0x9fc00000..0x9fffffff size 0x00400000 (pgdir) D/TC:0 dump_mmap_table:921 type TA_RAM va 0x99c00000..0x9adfffff pa 0x9ea00000..0x9fbfffff size 0x01200000 (pgdir) D/TC:0 dump_mmap_table:921 type IO_SEC va 0x9b000000..0x9b1fffff pa 0x4d000000..0x4d1fffff size 0x00200000 (pgdir) D/TC:0 dump_mmap_table:921 type IO_SEC va 0x9b200000..0x9b5fffff pa 0x4a400000..0x4a7fffff size 0x00400000 (pgdir) D/TC:0 dump_mmap_table:921 type IO_NSEC va 0x9b600000..0x9b7fffff pa 0x02800000..0x029fffff size 0x00200000 (pgdir) D/TC:0 dump_mmap_table:921 type IO_SEC va 0x9b800000..0x9b9fffff pa 0x01800000..0x019fffff size 0x00200000 (pgdir) D/TC:0 dump_mmap_table:921 type RES_VASPACE va 0x9ba00000..0x9c3fffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir) D/TC:0 dump_mmap_table:921 type SHM_VASPACE va 0x9c600000..0x9e5fffff pa 0x00000000..0x01ffffff size 0x02000000 (pgdir) D/TC:0 dump_mmap_table:921 type TEE_RAM_RX va 0x9e800000..0x9e874fff pa 0x9e800000..0x9e874fff size 0x00075000 (smallpg) D/TC:0 dump_mmap_table:921 type TEE_RAM_RW va 0x9e875000..0x9e9fffff pa 0x9e875000..0x9e9fffff size 0x0018b000 (smallpg) D/TC:0 core_mmu_xlat_table_alloc:527 xlat tables used 1 / 8 D/TC:0 core_mmu_xlat_table_alloc:527 xlat tables used 2 / 8 I/TC: I/TC: OP-TEE version custom: 4.3.0-125-g55a4d8393-dev (gcc version 11.3.1 20220712 (Arm GNU Toolchain 11.3.Rel1)) #1 Wed Se4 I/TC: WARNING: This OP-TEE configuration might be insecure! I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html I/TC: Primary CPU initializing D/TC:0 0 boot_init_primary_late:1011 Executing at offset 0 with virtual load address 0x9e800000 I/TC: GIC redistributor base address not provided I/TC: Assuming default GIC group status and modifier D/TC:0 0 do_init_calls:19 preinitcall level 2 mobj_mapped_shm_init() D/TC:0 0 mobj_mapped_shm_init:467 Shared memory address range: 9c600000, 9e600000 D/TC:0 0 do_init_calls:19 early_initcall level 1 teecore_init_pub_ram() D/TC:0 0 do_init_calls:19 early_initcall level 2 init_ti_sci() D/TC:0 0 k3_sec_proxy_init:243 tx_thread: 11, rx_thread: 10 F/TC:0 0 k3_sec_proxy_send:131 Verifying the thread F/TC:0 0 k3_sec_proxy_verify_thread:71 Check for thread corruption F/TC:0 0 k3_sec_proxy_verify_thread:88 Check for thread direction F/TC:0 0 k3_sec_proxy_verify_thread:100 Check for thread queue F/TC:0 0 k3_sec_proxy_verify_thread:113 Success F/TC:0 0 k3_sec_proxy_recv:193 Verifying thread F/TC:0 0 k3_sec_proxy_verify_thread:71 Check for thread corruption F/TC:0 0 k3_sec_proxy_verify_thread:88 Check for thread direction F/TC:0 0 k3_sec_proxy_verify_thread:100 Check for thread queue F/TC:0 0 k3_sec_proxy_verify_thread:113 Success I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.6--v09.01.06 (Kool Koala)') D/TC:0 0 do_init_calls:19 service_initcall level 1 tee_cryp_init() D/TC:0 0 do_init_calls:19 service_initcall level 2 check_ta_store() D/TC:0 0 check_ta_store:449 TA store: "Secure Storage TA" D/TC:0 0 check_ta_store:449 TA store: "REE" D/TC:0 0 do_init_calls:19 service_initcall level 2 verify_pseudo_tas_conformance() D/TC:0 0 do_init_calls:19 service_initcall level 3 secure_boot_information() F/TC:0 0 k3_sec_proxy_send:131 Verifying the thread F/TC:0 0 k3_sec_proxy_verify_thread:71 Check for thread corruption F/TC:0 0 k3_sec_proxy_verify_thread:88 Check for thread direction F/TC:0 0 k3_sec_proxy_verify_thread:100 Check for thread queue F/TC:0 0 k3_sec_proxy_verify_thread:113 Success F/TC:0 0 k3_sec_proxy_recv:193 Verifying thread F/TC:0 0 k3_sec_proxy_verify_thread:71 Check for thread corruption F/TC:0 0 k3_sec_proxy_verify_thread:88 Check for thread direction F/TC:0 0 k3_sec_proxy_verify_thread:100 Check for thread queue F/TC:0 0 k3_sec_proxy_verify_thread:113 Success E/TC:0 0 ti_sci_get_response:123 Message not acknowledged E/TC:0 0 ti_sci_do_xfer:154 Error, access denied : -65535 F/TC:0 0 k3_sec_proxy_send:131 Verifying the thread F/TC:0 0 k3_sec_proxy_verify_thread:71 Check for thread corruption F/TC:0 0 k3_sec_proxy_verify_thread:88 Check for thread direction F/TC:0 0 k3_sec_proxy_verify_thread:100 Check for thread queue F/TC:0 0 k3_sec_proxy_verify_thread:113 Success F/TC:0 0 k3_sec_proxy_recv:193 Verifying thread F/TC:0 0 k3_sec_proxy_verify_thread:71 Check for thread corruption F/TC:0 0 k3_sec_proxy_verify_thread:88 Check for thread direction F/TC:0 0 k3_sec_proxy_verify_thread:100 Check for thread queue F/TC:0 0 k3_sec_proxy_verify_thread:113 Success E/TC:0 0 ti_sci_get_response:123 Message not acknowledged E/TC:0 0 ti_sci_do_xfer:154 Error, access denied : -65535 D/TC:0 0 do_init_calls:19 service_initcall level 3 tee_fs_init_key_manager() F/TC:0 0 k3_sec_proxy_send:131 Verifying the thread F/TC:0 0 k3_sec_proxy_verify_thread:71 Check for thread corruption F/TC:0 0 k3_sec_proxy_verify_thread:88 Check for thread direction F/TC:0 0 k3_sec_proxy_verify_thread:100 Check for thread queue F/TC:0 0 k3_sec_proxy_verify_thread:113 Success F/TC:0 0 k3_sec_proxy_recv:193 Verifying thread F/TC:0 0 k3_sec_proxy_verify_thread:71 Check for thread corruption F/TC:0 0 k3_sec_proxy_verify_thread:88 Check for thread direction F/TC:0 0 k3_sec_proxy_verify_thread:100 Check for thread queue F/TC:0 0 k3_sec_proxy_verify_thread:113 Success E/TC:0 0 ti_sci_get_response:123 Message not acknowledged E/TC:0 0 ti_sci_do_xfer:154 Error, access denied : -65535 E/TC:0 0 ti_sci_get_dkek:349 Error transfert E/TC:0 0 tee_otp_get_hw_unique_key:103 Could not get HUK, with error : ffff0001 E/TC:0 0 do_init_calls:22 service_initcall __text_start + 0x000747a0 failed D/TC:0 0 do_init_calls:19 driver_initcall level 2 init_multi_core_panic_handler() D/TC:0 0 do_init_calls:19 driver_initcall level 2 mobj_init() D/TC:0 0 do_init_calls:19 driver_initcall level 2 default_mobj_init() D/TC:0 0 do_init_calls:19 driver_initcall level 3 gic_set_primary_done() I/TC: Primary CPU switching to normal world boot U-Boot SPL 2023.04-dirty (Sep 18 2024 - 11:56:54 +0200)
SBL code :
/*
* Copyright (C) 2018-2022 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <string.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"
#include <drivers/sciclient.h>
#include <drivers/bootloader.h>
#define BOOTLOADER_SD_APPIMAGE_FILENAME ("/sd0/app")
#define BOOTLOADER_SD_LINUX ("/sd0/app_linux")
#define BOOTLOADER_APPIMAGE_LINUX_MAX_FILE_SIZE (0x800000) /* Size of section MSRAM_2 specified in linker.cmd */
#define BOOTLOADER_APPIMAGE_MAX_FILE_SIZE (0x60000) /* Size of section MSRAM_2 specified in linker.cmd */
uint8_t gAppImageBufLinux[BOOTLOADER_APPIMAGE_LINUX_MAX_FILE_SIZE] __attribute__((aligned(4096), section(".bss.app")));
uint8_t gAppImageBuf[BOOTLOADER_APPIMAGE_MAX_FILE_SIZE] __attribute__((aligned(128), section(".bss.filebuf")));
/* call this API to stop the booting process and spin, do that you can connect
* debugger, load symbols and then make the 'loop' variable as 0 to continue execution
* with debugger connected.
*/
void loop_forever(void)
{
volatile uint32_t loop = 1;
while(loop)
;
}
int main(void)
{
int32_t status;
Bootloader_profileReset();
Bootloader_socWaitForFWBoot();
#ifndef DISABLE_WARM_REST_WA
/* Warm Reset Workaround to prevent CPSW register lockup */
if (!Bootloader_socIsMCUResetIsoEnabled())
{
Bootloader_socResetWorkaround();
}
#endif
Bootloader_profileAddProfilePoint("SYSFW init");
if (!Bootloader_socIsMCUResetIsoEnabled())
{
/* Update devGrp to ALL to initialize MCU domain when reset isolation is
not enabled */
Sciclient_BoardCfgPrms_t boardCfgPrms_pm =
{
.boardConfigLow = (uint32_t)0,
.boardConfigHigh = 0,
.boardConfigSize = 0,
.devGrp = DEVGRP_ALL,
};
status = Sciclient_boardCfgPm(&boardCfgPrms_pm);
Sciclient_BoardCfgPrms_t boardCfgPrms_rm =
{
.boardConfigLow = (uint32_t)0,
.boardConfigHigh = 0,
.boardConfigSize = 0,
.devGrp = DEVGRP_ALL,
};
status = Sciclient_boardCfgRm(&boardCfgPrms_rm);
/* Enable MCU PLL. MCU PLL will not be enabled by DMSC when devGrp is set
to Main in boardCfg */
Bootloader_enableMCUPLL();
}
Bootloader_socOpenFirewalls();
Bootloader_socNotifyFirewallOpen();
System_init();
Bootloader_profileAddProfilePoint("System_init");
Drivers_open();
Bootloader_profileAddProfilePoint("Drivers_open");
DebugP_log("\r\n");
DebugP_log("Starting SD Bootloader ... \r\n");
status = Board_driversOpen();
DebugP_assert(status == SystemP_SUCCESS);
Bootloader_profileAddProfilePoint("Board_driversOpen");
status = Sciclient_getVersionCheck(1);
Bootloader_profileAddProfilePoint("Sciclient Get Version");
/* File I/O */
if(SystemP_SUCCESS == status)
{
/* Open app file */
FF_FILE *appFp = ff_fopen(BOOTLOADER_SD_APPIMAGE_FILENAME, "rb");
/* Check if file open succeeded */
if(appFp == NULL)
{
status = SystemP_FAILURE;
DebugP_log("Cant open file from sd card\r\n");
}
else
{
/* Check file size */
uint32_t fileSize = ff_filelength(appFp);
if(fileSize >= BOOTLOADER_APPIMAGE_MAX_FILE_SIZE)
{
/* Application size more than buffer size, abort */
status = SystemP_FAILURE;
DebugP_log("Appimage size exceeded limit !!\r\n");
}
else
{
/* Read the file into RAM buffer */
ff_fread(gAppImageBuf, fileSize, 1, appFp);
}
/* Close the file */
ff_fclose(appFp);
}
}
if(SystemP_SUCCESS == status)
{
/* Open app file */
FF_FILE *appFpLinux = ff_fopen(BOOTLOADER_SD_LINUX, "rb");
/* Check if file open succeeded */
if(appFpLinux == NULL)
{
status = SystemP_FAILURE;
DebugP_log("Cant open linux file from sd card\r\n");
}
else
{
/* Check file size */
uint32_t fileSize = ff_filelength(appFpLinux);
if(fileSize >= BOOTLOADER_APPIMAGE_LINUX_MAX_FILE_SIZE)
{
/* Application size more than buffer size, abort */
status = SystemP_FAILURE;
DebugP_log("Appimage size exceeded limit !!\r\n");
}
else
{
/* Read the file into RAM buffer */
ff_fread(gAppImageBufLinux, fileSize, 1, appFpLinux);
}
/* Close the file */
ff_fclose(appFpLinux);
}
}
Bootloader_profileAddProfilePoint("File read from SD card");
if(SystemP_SUCCESS == status)
{
DebugP_log("Files read from sd card\r\n");
Bootloader_BootImageInfo bootImageInfo;
Bootloader_Params bootParams;
Bootloader_Handle bootHandle;
Bootloader_BootImageInfo bootImageInfo_Linux;
Bootloader_Params bootParams_Linux;
Bootloader_Handle bootHandle_Linux;
Bootloader_Params_init(&bootParams);
Bootloader_Params_init(&bootParams_Linux);
Bootloader_BootImageInfo_init(&bootImageInfo);
Bootloader_BootImageInfo_init(&bootImageInfo_Linux);
bootParams.memArgsAppImageBaseAddr = (uintptr_t)gAppImageBuf;
bootParams_Linux.memArgsAppImageBaseAddr = (uintptr_t)gAppImageBufLinux;
bootHandle = Bootloader_open(CONFIG_BOOTLOADER_MEM, &bootParams);
if(bootHandle != NULL)
{
/* Initialize PRU Cores if applicable */
Bootloader_Config *cfg = (Bootloader_Config *)bootHandle;
if(TRUE == cfg->initICSSCores)
{
status = Bootloader_socEnableICSSCores(BOOTLOADER_ICSS_CORE_DEFAULT_FREQUENCY);
DebugP_assert(status == SystemP_SUCCESS);
}
status = Bootloader_parseMultiCoreAppImage(bootHandle, &bootImageInfo);
if(status == SystemP_SUCCESS)
{
DebugP_log("Multicore image parsing is OK\r\n");
}
else
{
DebugP_log("Multicore image parsing went wrong\r\n");
}
/* Load CPUs */
/* Do not load M4 when MCU domain is reset isolated */
if (!Bootloader_socIsMCUResetIsoEnabled())
{
if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_M4FSS0_0)))
{
bootImageInfo.cpuInfo[CSL_CORE_ID_M4FSS0_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_M4FSS0_0);
Bootloader_profileAddCore(CSL_CORE_ID_M4FSS0_0);
status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_M4FSS0_0]);
}
}
if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_0)))
{
bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS1_0);
Bootloader_profileAddCore(CSL_CORE_ID_R5FSS1_0);
status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0]);
}
if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_1)))
{
bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_1].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS1_1);
Bootloader_profileAddCore(CSL_CORE_ID_R5FSS1_1);
status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_1]);
}
/* Assume self boot for either of the cores of R50 cluster */
uint32_t isSelfBoot = FALSE;
if(TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS0_0))
{
isSelfBoot = TRUE;
Bootloader_profileAddCore(CSL_CORE_ID_R5FSS0_0);
}
if(TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS0_1))
{
isSelfBoot = TRUE;
Bootloader_profileAddCore(CSL_CORE_ID_R5FSS0_1);
}
/* Self cores has to be reset together, so check for both */
if(status == SystemP_SUCCESS && (TRUE == isSelfBoot))
{
/* Set clocks for self cluster */
bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS0_0);
bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_1].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS0_1);
/* Reset self cluster, both Core0 and Core 1. Init RAMs and load the app */
/* Skip the image load by passing TRUE, so that image load on self core doesnt corrupt the SBLs IVT. Load the image later before the reset release of the self core */
status = Bootloader_loadSelfCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0], TRUE);
if((status == SystemP_SUCCESS) && (TRUE == Bootloader_socIsR5FSSDual(BOOTLOADER_R5FSS0)))
{
status = Bootloader_loadSelfCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_1], FALSE);
}
}
Bootloader_profileAddProfilePoint("CPU load");
Bootloader_profileUpdateAppimageSize(Bootloader_getMulticoreImageSize(bootHandle));
Bootloader_profileUpdateMediaAndClk(BOOTLOADER_MEDIA_SD, 0);
}
else
{
status = SystemP_FAILURE;
}
bootHandle_Linux = Bootloader_open(CONFIG_BOOTLOADER_LINUX, &bootParams_Linux);
if(bootHandle_Linux != NULL)
{
/* Initialize PRU Cores if applicable */
//Bootloader_Config *cfgLinux = (Bootloader_Config *)bootHandle_Linux;
status = Bootloader_parseAndLoadLinuxAppImage(bootHandle_Linux, &bootImageInfo_Linux);
if(status == SystemP_SUCCESS)
{
DebugP_log("Linux app image parsing is OK\r\n");
}
else
{
DebugP_log("Linux app image parsing went wrong\r\n");
}
if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle_Linux, CSL_CORE_ID_A53SS0_0)))
{
bootImageInfo_Linux.cpuInfo[CSL_CORE_ID_A53SS0_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_A53SS0_0);
Bootloader_profileAddCore(CSL_CORE_ID_A53SS0_0);
status = Bootloader_loadCpu(bootHandle_Linux, &bootImageInfo_Linux.cpuInfo[CSL_CORE_ID_A53SS0_0]);
}
Bootloader_profileUpdateAppimageSize(Bootloader_getMulticoreImageSize(bootHandle_Linux));
}
else
{
status = SystemP_FAILURE;
}
if(status == SystemP_SUCCESS)
{
/* Print SBL Profiling logs to UART as other cores may use the UART for logging */
Bootloader_profileAddProfilePoint("SBL End");
Bootloader_profilePrintProfileLog();
DebugP_log("Image loading done, switching to application ...\r\n");
UART_flushTxFifo(gUartHandle[CONFIG_UART0]);
}
SOC_unlockAllMMR();
status = Bootloader_runCpu(bootHandle_Linux, &bootImageInfo_Linux.cpuInfo[CSL_CORE_ID_A53SS0_0]);
if (!Bootloader_socIsMCUResetIsoEnabled())
{
if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_M4FSS0_0)))
{
status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_M4FSS0_0]);
}
}
if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_0)))
{
status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0]);
}
if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_1)))
{
status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_1]);
}
if(status == SystemP_SUCCESS)
{
/* Load the image on self core now */
if( bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0].rprcOffset != BOOTLOADER_INVALID_ID)
{
status = Bootloader_rprcImageLoad(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0]);
}
/* Reset self cluster, both Core0 and Core 1. Init RAMs and run the app */
status = Bootloader_runSelfCpu(bootHandle, &bootImageInfo);
}
/* it should not return here, if it does, then there was some error */
Bootloader_close(bootHandle);
}
if(status != SystemP_SUCCESS)
{
DebugP_log("Some tests have failed!!\r\n");
}
Drivers_close();
System_deinit();
return 0;
}
Thanks for your help !
Best regards,
Baptiste C
