DDR2: Exact routing specification for OMAP L138?

Michael,

I got it, thanks.

Zheng

Michael,

I have some following-up questions:

L138 datasheet page [127-139] contains specifications on many aspects of DDR2/mDDR memory. However, on the important specification of trace impedance, only on page 131, Table 5-29 did I find numeric information, yet it is only for single-ended traces:

For (DDR_CLKP, DDR_CLKN) pair which from EVMAM1808 layout and Gerber file we could see having differential impedance of 100Ω, there is no information in L138 datasheet specifying the required differential impedance. What I only found was Table 5-33, which defined (DDR_CLKP, DDR_CLKN) as belong to clock net class CK, but this is not an electrical specification.

Although it is almost guaranteed that EVMAM1808's 100Ω value is correct, I would still like to find this specification from TI documents for added assurance. Where can I get it?

Zheng

Impedance of the DDR differential signals is specified by the single ended impedance and the requirement to route the differential pair at 2x center to center spacing.  The absolute impedance value is not as important as routing the signals close together to maximize noise rejection.

-Mike

Michael,

Michael Shust said:

route the differential pair at 2x center to center spacing.

I don't really understand this. Could you explain what is "2x center to center spacing"?

Zheng

Michael,

I got it, thanks very much for explanation.

Zheng

Michael,

In EVMAM1808 board layout file I found the following requirements:

I noted two points:

Z₀:

By the above standard formula for single-ended and differential impedance which can be found at Impedance Calculators - Mantaro Product Development Services, Z_diff would never be exactly 2Z₀ unless d/h=∞, which requires h→0. The ratio of 2:1 = 100:50 in EVMAM1808 is by using width different than single-ended traces (5.1_diff  vs 5.0_single-ended). This however violated the rule you gave in two aspects:

Does it matter or not?

Minimum impedance

In L138 datasheet table 5-29, the minimum of Z₀ would be 50Ω. However, EVMAM1808 specified nominal 50Ω impedance for Z₀. Some PCB manufacturers told me that they could only guarantee the impedance fall within ±10% of the nominal range. So if -10% happens the actual Z₀ would be 45Ω, below the minimum requirement.

1. Would an actual 45Ω cause problem for DDR?
2. Do I have to consider this tolerance in board fabrication to specify Z_0-nominal × (1-10%) ≥ 50Ω ⟹ Z_0-nominal ≥ 55.6Ω?

Shape

As already mentioned above, EVMAM1808 uses unequal w and d which is different from your rule. Manufacturers also suggested adjusting w and d with like (d=4.8, w=5.2) and other values with even larger difference between w and d values. I don’t know the physics here, but is there any rigid rule requiring w = d here, or unequal values can be used to obtain required Z_diff as defined in formula [1] above?

Trapezoidal trace

Manufacturers told me that due to the etching process, all traces would eventually have trapezoidal shape. The following illustration is from Polar instruments:

With this real-world trapezoidal shape, do you define w = (w1 + w2) / 2 ? Do you measure d in Z_diff from bottom or middle of the traces? Is there still any requirement for w = d?

Zheng

The controlling spec is the OMAP-L138 data sheet.

The PCB fab shop will handle getting the correct PCB dimensions to hit the impedance spec from the data sheet.  That is one of the things you are paying them for.

I think you are overcomplicating this.

-Mike 

Michael,

I will discuss with PCB fab houses on this.

Zheng