AM625: reading GTC counter from M4F caused exception

Hi Jim,

I have another thread where I wrote about GTC and how to use it properly. Although on AM64x, but still would apply for AM62x. The response on that thread is as follows:

The GTC is supposed to continue from the last count value it had (even upon JTAG reset). This is mentioned in the AM64x TRM, I have attached a snippet. It would be helpful if you go through it.

Additionally I think you needed the GTC counter value to reset to zero upon soft reset, hence I have written a small application which will do the same upon JTAG reset + after you run the application.

In the above screenshot, there are 4 steps mentioned(in the comments inside code below) which I have implemented and I would encourage you to use the flow mentioned in the attached C file to reset the counter value to 0.

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#include <stdio.h>
#include <kernel/dpl/DebugP.h>
#include <inttypes.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"
#include <drivers/gtc.h>
#include <drivers/soc.h>
#include <drivers/gtc/v0/cslr_gtc.h>
#include <kernel/dpl/ClockP.h>

/*
 * This is an empty project provided for all cores present in the device.
 * User can use this project to start their application by adding more SysConfig modules.
 *
 * This application does driver and board init and just prints the pass string on the console.
 * In case of the main core, the print is redirected to the UART console.
 * For all other cores, CCS prints are used.
 */

void GTC_disable(void);
void GTC_clearCountRegisters(void);

void hello_world_main(void *args)
{
    int32_t retVal = SystemP_SUCCESS;
    uint64_t gtcCount1 = 0, gtcCount2 = 0;
    uint64_t clkRate = 0;

    /* Open drivers to open the UART driver for console */
    Drivers_open();
    Board_driversOpen();

    // This API is called to reset the 0th and 1st bit of the GTC0_GTC_CFG1_GTC_CFG1_CNTCR register
    GTC_disable();
    // Now clear the GTC0_GTC_CFG1_GTC_CFG1_CNTCV_LO and GTC0_GTC_CFG1_GTC_CFG1_CNTCV_HI registers
    GTC_clearCountRegisters();

    retVal = GTC_init();
    DebugP_assert(SystemP_SUCCESS == retVal);

    retVal = SOC_moduleGetClockFrequency(TISCI_DEV_GTC0, TISCI_DEV_GTC0_GTC_CLK, &clkRate);
    DebugP_assert(SystemP_SUCCESS == retVal);

    gtcCount1 = GTC_getCount64();

    ClockP_sleep(3);

    gtcCount2 = GTC_getCount64();

    DebugP_log("%lf is the time taken in seconds for testing GTC!!!\r\n",((Float64)((Float64)gtcCount2 - (Float64)gtcCount1) / (Float64)clkRate));

    Board_driversClose();
    Drivers_close();
}


void GTC_disable(void)
{
    uint32_t baseAddr = (uint32_t) AddrTranslateP_getLocalAddr(CSL_GTC0_GTC_CFG1_BASE);

    HW_WR_REG32(baseAddr, 0);

    return;
}
void GTC_clearCountRegisters(void)
{
    uint32_t baseAddr = (uint32_t) AddrTranslateP_getLocalAddr(CSL_GTC0_GTC_CFG1_BASE);

    HW_WR_REG32(baseAddr + CSL_GTC_CFG1_CNTCV_LO, 0); // Firstly, setting LO to 0
    HW_WR_REG32(baseAddr + CSL_GTC_CFG1_CNTCV_HI, 0); // Secondly, setting HI to 0

    return;
}

Let me know if this helps you resolve your issue.

Regards,

Vaibhav