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DRA821U: Cortex-A72 access to 48-bit address space in AArch32 mode

GerryL
Intellectual 640 points
Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

Tool/software:

Hi,

What is the intended method of mapping into the system 48-bit address space when running an A72 in AArch32 mode?

The R5F's have RAT modules to do this, but apparently not the A72's.

I'm sure I must be missing something obvious, so I would appreciate greatly if someone could point me in the right direction!

Thanks,
Gerry

  • 0
    TI__Mastermind 23805 points

    Hello,

    While each virtual address space in AARCH32 is 32-bits it can access up to 40-bits of physical address space using its MMU.  If you use LPAE w/EAE=40bit you can create a 32-bit virtual handle to access any of the SOC system memory regions in DRA821 (highest address is < 40bit).   In AARCH64 mode the A72 can map 48-bit virtual handle to its 44-bit physical limit.  The SOC bus can handle 48 bit addresses, those ~extra bits allow virtual addresses to flow for alternate address spaces.   For straightforward code the 40 bits should enough to get all the resources.  If more are needed go to AARCH64 mode.  TI's SDK for Linux/QNX/... will using AARCH64.  I've seen some custom industrial use AARCH32 for compatibility and don't recall any issues.

    Regards,
    Richard W.
  • 0 in reply to Richard Woodruff
    Intellectual 640 points

    Hi Richard,

    Thanks for that.  So it seems that I did miss something obvious -- duh!!  My tired old brain still thinks of MMUs as being just for memory.  I do hope I don't lose any "Intellectual" points Disappointed

    Btw, I did find that cslr_soc_baseaddress.h has all base addresses nicely defined, and as you point out, all < 40 bit.

    Cheers,
    Gerry