AM6442: Sysconfig generating incompatible clock configurations for PRU_ICSS0/1

Tool/software:

SDK: Industrial communications v11.0.0.08

SysConfig 1.22.0+3893

In my current project both PRU_ICSS are used:

- PRU_ICSS0 is configured for RF50_0, as an Ethercat dependency.

- PRU_ICSS1 is configured for the RF51_0 core.

They run at different clock rates, but sysconfig is assigning the same parent clock for both (=2 in this case). This leads to one on them not working as intended: if I delay the startup of RF51_0, I can verify that ICSS0 runs OK, but "breaks" right after calling PowerClock_init().

/* Core R5F0_0 */
SOC_ModuleClockFrequency gSocModulesClockFrequency[] = {
    { TISCI_DEV_PRU_ICSSG0, TISCI_DEV_PRU_ICSSG0_CORE_CLK, 200000000,2},
    { TISCI_DEV_PRU_ICSSG0, TISCI_DEV_PRU_ICSSG0_UCLK_CLK, 192000000, SOC_MODULES_END},
    { TISCI_DEV_PRU_ICSSG0, TISCI_DEV_PRU_ICSSG0_IEP_CLK, 200000000,5},

    { SOC_MODULES_END, SOC_MODULES_END, SOC_MODULES_END, SOC_MODULES_END },
};

/* Core R5F1_0 */
SOC_ModuleClockFrequency gSocModulesClockFrequency[] = {

    { TISCI_DEV_PRU_ICSSG1, TISCI_DEV_PRU_ICSSG1_CORE_CLK, 333333333,2},
    { TISCI_DEV_PRU_ICSSG1, TISCI_DEV_PRU_ICSSG1_UCLK_CLK, 192000000, SOC_MODULES_END},
    { TISCI_DEV_PRU_ICSSG1, TISCI_DEV_PRU_ICSSG1_IEP_CLK, 200000000,5},

    { SOC_MODULES_END, SOC_MODULES_END, SOC_MODULES_END, SOC_MODULES_END },
};