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The tables below highlight the working configurations of custom OSPI and QSPI serial NOR/NAND Flash Parts
Note: After using the values for the Flash part present in the below tables, run the OSPI Flash IO example to verify if Flash operations are working as expected.
To get the values for the right Flash Part, simply search for the Name in this FAQ.
Working Flash configurations of Winbond Serial NAND Flash parts
|
Flash Part Name |
|||||
|
W35N01JWTBAG |
W35N01JWTBAG |
||||
|
SoC tested on |
AM62A |
AM62A |
|||
|
Flash Parameters |
OSPI |
OSPI |
|||
|
Serial Flash Configuration |
Flash Type |
Serial Nand Flash |
Serial Nand Flash |
||
|
Flash Name |
W35N01JWTBAG |
W35N01JWTBAG |
|||
|
Protocol |
1S-8S-8S |
8D-8D-8D |
|||
|
Basic Flash Configuration |
Flash Size in Bytes |
134217728 |
134217728 |
||
|
Flash Page Size in Bytes |
4096 |
4096 |
|||
|
Flash JEDEC Manufacturer ID |
0xEF |
0xEF |
|||
|
Flash JEDEC Device ID |
0xDC21 |
0xDC21 |
|||
|
Page Load Command |
0x13 |
0x13 |
|||
|
Page Program Command |
0x10 |
0x10 |
|||
|
Erase Configurations |
Flash Block Size In Bytes |
262144 |
262144 |
||
|
Block Erase CMD |
0xD8 |
0xD8 |
|||
|
Protocol Enable Configuration |
Read Command |
0xCB |
0x9D |
||
|
Write/Page Program Command |
0xC4 |
0x84 |
|||
|
Dummy Clocks (CMD) |
8 |
8 |
|||
|
Dummy Clocks (READ) |
20 |
8 |
|||
|
Protocol Configuration |
Config Is Via Addressed Reg |
Yes |
Yes |
||
|
Address Of Config Reg |
0x0 |
0x0 |
|||
|
CMD To Read Config Reg |
0x85 |
0x85 |
|||
|
CMD To Write To Config Reg |
0x81 |
0x81 |
|||
|
Register Data |
Data Shift Bits |
0 |
0 |
||
|
Data Binary Mask |
0xFF |
0xFF |
|||
|
Data To Be Written |
223 |
231 |
|||
|
Dummy Cycle Configuration |
Config Is Via Addressed Reg |
Yes |
Yes |
||
|
Address Of Config Reg |
0x01 |
0x01 |
|||
|
CMD To Read Config Reg |
0x85 |
0x85 |
|||
|
CMD To Write To Config Reg |
0x81 |
0x81 |
|||
|
Register Data |
Data Shift Bits |
0 |
0 |
||
|
Data Binary Mask |
0xFF |
0xFF |
|||
|
Data To Be Written |
20 |
8 |
|||
|
JEDEC ID Read Configuration |
Read ID CMD |
0x9F |
0x9F |
||
|
Number Of Bytes To Read |
3 |
3 |
|||
|
Advanced Flash Configuration |
Flash Reset Type |
0x10 |
0x10 |
||
|
Write Enable CMD |
0x06 |
0x06 |
|||
|
Read Status Register CMD |
0x0F |
0x0F |
|||
|
Write Status Register CMD |
0x1F |
0x1F |
|||
|
WIP Status Reg Addr |
0xC0 |
0xC0 |
|||
|
WIP Bit |
0 |
0 |
|||
|
WIP Read CMD (xSPI) |
0x0F |
0x0F |
|||
|
WIP Status Reg Addr (xSPI) |
0x0000C000 |
0x0000C000 |
|||
|
WIP Read Status Dummy Cycle (xSPI) |
7 |
7 |
|||
|
Flash Busy Timeout |
256000000 |
256000000 |
|||
|
Page Program Timeout |
512 |
512 |
|||
|
Program Status Register Address |
0xC0 |
0xC0 |
|||
|
Program Status Register Addr (xSPI) |
0x0000C000 |
0x0000C000 |
|||
|
Program Status Bit Position |
3 |
3 |
|||
|
Erase Status Register Address |
0xC0 |
0xC0 |
|||
|
Erase Status Register Address (xSPI) |
0x0000C000 |
0x0000C000 |
|||
|
Erase Status Bit Position |
2 |
2 |
|||
|
Write Protection Status Reg Address |
0xA0 |
0xA0 |
|||
|
Write Protection Status Mask |
255 |
255 |
|||
|
Command Extension Type |
REPEAT |
REPEAT |
|||
|
Input Clock Frequency (Hz) |
166666666 |
200000000 |
|||
|
Input Clock Divider |
8 |
8 |
|||
|
Enable DMA |
Yes |
Yes |
|||
|
Enable PHY Mode |
No |
No |
|||
Working Flash configurations of Winbond Serial NOR Flash parts
|
Flash Part Name |
|||||
|
W25Q128JW |
W25H512JV |
W25Q512JV |
W25Q256JVFQ |
||
| SoC tested on |
AM62x |
AM62x |
AM243x |
AM64x |
|
|
Flash Parameters |
QSPI |
QSPI |
QSPI |
QSPI |
|
|
Serial Flash Configuration |
Flash Type |
Serial Nor Flash |
Serial Nor Flash |
Serial Nor Flash |
Serial Nor Flash |
|
Flash Name |
W25Q128JW |
W25H512JV |
W25Q512JV |
W25Q256JVFQ |
|
|
Protocol |
1S-1S-4S |
1S-1S-4S |
1S-1S-4S |
1S-1S-4S |
|
|
Basic Flash Configuration |
Flash Size in Bytes |
16777216 |
67108864 |
67108864 |
33554432 |
|
Flash Page Size in Bytes |
256 |
256 |
256 |
256 |
|
|
Flash JEDEC Manufacturer ID |
0xEF |
0xEF |
0xEF |
0xEF |
|
|
Flash JEDEC Device ID |
0x6018 |
0x9020 |
0x4020 |
0x7019 |
|
|
Erase Configurations |
Flash Block Size In Bytes |
32768 |
65536 |
65536 |
65536 |
|
Flash Sector Size In Bytes |
4096 |
4096 |
4096 |
4096 |
|
|
Block Erase CMD (3B) |
0x52 |
0xD8 |
0xD8 |
0xD8 |
|
|
Block Erase CMD (4B) |
0x52 |
0xDC |
0xDC |
0xD8 |
|
|
Sector Erase CMD (3B) |
0x20 |
0x20 |
0x20 |
0x20 |
|
|
Sector Erase CMD (4B) |
0x20 |
0x21 |
0x21 |
0x20 |
|
|
Protocol Enable Configuration |
Read Command |
0x6B |
0x6C |
0x6C |
0x6C |
|
Write/Page Program Command |
0x32 |
0x34 |
0x34 |
0x32 |
|
|
Mode Clocks (CMD) |
0 |
0 |
0 |
0 |
|
|
Mode Clocks (READ) |
0 |
0 |
0 |
0 |
|
|
Dummy Clocks (CMD) |
0 |
0 |
0 |
0 |
|
|
Dummy Clocks (READ) |
8 |
8 |
8 |
8 |
|
|
Quad Enable Type |
6 |
6 |
6 |
4 |
|
|
Octal Enable Type |
0 |
0 |
0 |
0 |
|
|
QPI Sequence |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
OPI Sequence |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
Protocol Configuration |
Config Is Via Addressed Reg |
No |
No |
No |
No |
|
Address Of Config Reg |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
CMD To Read Config Reg |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
CMD To Write To Config Reg |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
Register Data |
Data Shift Bits |
0 |
0 |
0 |
0 |
|
Data Binary Mask |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
Data To Be Written |
0 |
0 |
0 |
0 |
|
|
Dummy Cycle Configuration |
Config Is Via Addressed Reg |
No |
No |
No |
No |
|
Address Of Config Reg |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
CMD To Read Config Reg |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
CMD To Write To Config Reg |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
Register Data |
Data Shift Bits |
0 |
0 |
0 |
0 |
|
Data Binary Mask |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
Data To Be Written |
0 |
0 |
0 |
0 |
|
|
STR/DTR Configuration |
Address Of Config Reg |
0x00 |
0x00 |
0x00 |
0x00 |
|
CMD To Read Config Reg |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
CMD To Write To Config Reg |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
Register Data |
Data Shift Bits |
0 |
0 |
0 |
0 |
|
Data Binary Mask |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
Data To Be Written |
0 |
0 |
0 |
0 |
|
|
JEDEC ID Read Configuration |
Read ID CMD |
0x9F |
0x9F |
0x9F |
0x9F |
|
Number Of Bytes To Read |
3 |
3 |
3 |
3 |
|
|
Number Of Dummy Cycles In Quad Mode |
0 |
0 |
0 |
0 |
|
|
Number Of Dummy Cycles In Octal Mode |
0 |
0 |
0 |
4 |
|
|
Advanced Flash Configuration |
Flash Reset Type |
0x10 |
0x10 |
0x10 |
0x30 |
|
Flash Device Busy Type |
LEGACY POLLING OF SR |
LEGACY POLLING OF SR |
LEGACY POLLING OF SR |
LEGACY POLLING OF SR |
|
|
Write Enable CMD |
0x06 |
0x06 |
0x06 |
0x06 |
|
|
Read Status Register CMD |
0x05 |
0x05 |
0x05 |
0x05 |
|
|
WIP Bit |
0 |
0 |
0 |
0 |
|
|
WEL Bit |
1 |
1 |
1 |
1 |
|
|
WIP Read CMD (xSPI) |
0x00 |
0x00 |
0x00 |
0x05 |
|
|
WIP Status Reg Addr (xSPI) |
0x00 |
0x00 |
0x00 |
0x00 |
|
|
WIP Bit (xSPI) |
0 |
0 |
0 |
0 |
|
|
Chip Erase Command |
0xC7 |
0xC7 |
0xC7 |
0xC7 |
|
|
Flash Busy Timeout |
256000000 |
256000000 |
256000000 |
80000000 |
|
|
Page Program Timeout |
512 |
512 |
512 |
704 |
|
|
Enable 4 Byte Addressing |
No |
Yes |
Yes |
Yes |
|
|
Supported Addressing Modes |
1 |
1 |
1 |
1 |
|
|
4 Byte Addressing Enable Sequence |
0xA0 |
0xA0 |
0xA0 |
0xA5 |
|
|
Command Extension Type |
REPEAT |
NONE |
NONE |
NONE |
|
|
Input Clock Frequency (Hz) |
200000000 |
100000000 |
100000000 |
200000000 |
|
|
Input Clock Divider |
4 |
4 |
4 |
20 |
|
|
Enable DMA |
Yes |
No |
No |
Yes |
|
|
Enable PHY Mode |
No |
No |
No |
No |
|
Working Flash configurations of Cypress/Infineon Serial NOR Flash parts
|
Flash Part Name |
|||||
|
S28HS512T |
S25HL512T |
S25FL128SA |
|||
| SoC tested on |
Default Sitara EVMs |
AM243x-LP |
AM263x |
||
|
Flash Parameters |
OSPI |
QSPI |
QSPI |
||
|
Serial Flash Configuration |
Flash Type |
Serial NOR Flash |
Serial NOR Flash |
Serial NOR Flash |
|
|
Flash Name |
S28HS512T |
S25HL512T |
S25FL128SA |
||
|
Protocol |
8D-8D-8D |
4S-4D-4D |
1S-1S-4S |
||
|
Basic Flash Configuration |
Flash Size in Bytes |
67108864 |
67108864 |
16777216 |
|
|
Flash Page Size in Bytes |
256 |
256 |
256 |
||
|
Flash JEDEC Manufacturer ID |
0x34 |
0x34 |
0x01 |
||
|
Flash JEDEC Device ID |
0x5B1A |
0x2A1A |
0x2018 |
||
|
Erase Configurations |
Flash Block Size In Bytes |
262144 |
262144 |
65536 |
|
|
Flash Sector Size In Bytes |
4096 |
4096 |
4096 |
||
|
Block Erase CMD (3B) |
0xDC |
0xD8 |
0xD8 |
||
|
Block Erase CMD (4B) |
0xDC |
0xDC |
0xD8 |
||
|
Sector Erase CMD (3B) |
0x21 |
0x20 |
0x20 |
||
|
Sector Erase CMD (4B) |
0x21 |
0x21 |
0x20 |
||
|
Protocol Enable Configuration |
Read Command |
0xEE |
0xED |
0x6B |
|
|
Write/Page Program Command |
0x12 |
0x02 |
0x02 |
||
|
Mode Clocks (CMD) |
0 |
0 |
0 |
||
|
Mode Clocks (READ) |
0 |
1 |
0 |
||
|
Dummy Clocks (CMD) |
4 |
0 |
0 |
||
|
Dummy Clocks (READ) |
25 |
15 |
8 |
||
|
Quad Enable Type |
0 |
0 |
1 |
||
|
Octal Enable Type |
0 |
0 |
0 |
||
|
QPI Sequence |
0x00 |
0x08 |
0x00 |
||
|
OPI Sequence |
0x00 |
0x00 |
0x00 |
||
|
Protocol Configuration |
Config Is Via Addressed Reg |
Yes |
No |
No |
|
|
Address Of Config Reg |
0x00800006 |
0x00 |
0x00 |
||
|
CMD To Read Config Reg |
0x65 |
0x00 |
0x00 |
||
|
CMD To Write To Config Reg |
0x71 |
0x00 |
0x00 |
||
|
Register Data |
Data Shift Bits |
0 |
0 |
0 |
|
|
Data Binary Mask |
0x01 |
0x00 |
0x00 |
||
|
Data To Be Written |
1 |
0 |
0 |
||
|
Dummy Cycle Configuration |
Config Is Via Addressed Reg |
Yes |
Yes |
No |
|
|
Address Of Config Reg |
0x00800003 |
0x00800003 |
0x00 |
||
|
CMD To Read Config Reg |
0x65 |
0x65 |
0x00 |
||
|
CMD To Write To Config Reg |
0x71 |
0x71 |
0x00 |
||
|
Register Data |
Data Shift Bits |
0 |
0 |
0 |
|
|
Data Binary Mask |
0x0F |
0x0F |
0x00 |
||
|
Data To Be Written |
11 |
15 |
0 |
||
|
STR/DTR Configuration |
Config Is Via Addressed Reg |
Yes |
No |
No |
|
|
Address Of Config Reg |
0x00800006 |
0x00 |
0x00 |
||
|
CMD To Read Config Reg |
0x65 |
0x00 |
0x00 |
||
|
CMD To Write To Config Reg |
0x71 |
0x00 |
0x00 |
||
|
Register Data |
Data Shift Bits |
1 |
0 |
0 |
|
|
Data Binary Mask |
0x02 |
0x00 |
0x00 |
||
|
Data To Be Written |
1 |
0 |
0 |
||
|
JEDEC ID Read Configuration |
Read ID CMD |
0x9F |
0x9F |
0x00 |
|
|
Address Size (bytes) |
4 |
4 |
0 |
||
|
Number Of Bytes To Read |
3 |
3 |
0 |
||
|
Number Of Dummy Cycles In Quad Mode |
0 |
0 |
0 |
||
|
Number Of Dummy Cycles In Octal Mode |
4 |
4 |
0 |
||
|
Advanced Flash Configuration |
Flash Reset Type |
0x10 |
0x10 |
0x10 |
|
|
Flash Device Busy Type |
LEGACY POLLLING OF SR |
LEGACY POLLLING OF SR |
N/A |
||
|
Write Enable CMD |
0x06 |
0x06 |
0x06 |
||
|
Read Status Register CMD |
0x05 |
0x05 |
0x05 |
||
|
WIP Bit |
0 |
0 |
0 |
||
|
WEL Bit |
1 |
1 |
1 |
||
|
WIP Read CMD (xSPI) |
0x65 |
0x00 |
0x00 |
||
|
WIP Status Reg Addr (xSPI) |
0x00800000 |
0x00 |
0x00 |
||
|
WIP Bit (xSPI) |
0 |
0 |
0 |
||
|
Chip Erase Command |
0xC7 |
0xC7 |
0xC7 |
||
|
Flash Busy Timeout |
256000000 |
6000000 |
24000000 |
||
|
Page Program Timeout |
512 |
4000 |
4000 |
||
|
Enable 4 Byte Addressing |
Yes |
Yes |
No |
||
|
Supported Addressing Modes |
1 |
1 |
0 |
||
|
4 Byte Addressing Enable Sequence |
0xA1 |
0xA1 |
0 |
||
|
Command Extension Type |
REPEAT |
NONE |
NONE |
||
|
Input Clock Frequency (Hz) |
133333333 |
100000000 |
80000000 |
||
|
Input Clock Divider |
4 |
4 |
0 |
||
|
Enable DMA |
Yes |
Yes |
No |
||
|
Enable PHY Mode |
Yes |
Yes |
No |
||
Working Configurations of Macronix Serial NOR Flash parts
|
|
Flash Part Name |
|||
|
MX25UV125 |
MX25L25645gzni-08g |
MX25L3233F |
||
| SoC tested on |
AM62Px |
AM62x |
AM263Px |
|
|
Flash Parameters |
OSPI |
QSPI |
QSPI |
|
|
Serial Flash Configuration |
Flash Type |
Serial NOR Flash |
Serial NOR Flash |
Serial Nor Flash |
|
Flash Name |
MX25UV125 |
MX25L25645gzni-08g |
MX25L3233F |
|
|
Protocol |
8D-8D-8D |
4D-4D-4D |
1S-1S-4S |
|
|
Basic Flash Configuration |
Flash Size in Bytes |
16777216 |
33554432 |
4194304 |
|
Flash Page Size in Bytes |
256 |
256 |
256 |
|
|
Flash JEDEC Manufacturer ID |
0xC2 |
0xC2 |
0xC2 |
|
|
Flash JEDEC Device ID |
0x8138 |
0x2019 |
0x2016 |
|
|
Erase Configurations |
Flash Block Size In Bytes |
65536 |
65536 |
65536 |
|
Flash Sector Size In Bytes |
4096 |
4096 |
4096 |
|
|
Block Erase CMD (3B) |
0xD8 |
0xD8 |
0xD8 |
|
|
Block Erase CMD (4B) |
0xDC |
0xDC |
0xD8 |
|
|
Sector Erase CMD (3B) |
0x20 |
0x20 |
0x20 |
|
|
Sector Erase CMD (4B) |
0x21 |
0x21 |
0x20 |
|
|
Protocol Enable Configuration |
Read Command |
0xEE |
0xEB |
0x6B |
|
Write/Page Program Command |
0x12 |
0x02 |
0x02 |
|
|
Mode Clocks (CMD) |
0 |
0 |
0 |
|
|
Mode Clocks (READ) |
0 |
2 |
0 |
|
|
Dummy Clocks (CMD) |
4 |
0 |
0 |
|
|
Dummy Clocks (READ) |
16 |
4 |
8 |
|
|
Quad Enable Type |
0 |
2 |
2 |
|
|
Octal Enable Type |
0 |
0 |
0 |
|
|
QPI Sequence |
0x00 |
0x04 |
0xFF |
|
|
OPI Sequence |
0x00 |
0x00 |
0x00 |
|
|
Protocol Configuration |
Config Is Via Addressed Reg |
Yes |
No |
No |
|
Address Of Config Reg |
0x0 |
0x00 |
0x00 |
|
|
CMD To Read Config Reg |
0x71 |
0x00 |
0x00 |
|
|
CMD To Write To Config Reg |
0x72 |
0x00 |
0x00 |
|
|
Register Data |
Data Shift Bits |
0 |
0 |
0 |
|
Data Binary Mask |
0x03 |
0x00 |
0x00 |
|
|
Data To Be Written |
2 |
0 |
0 |
|
|
Dummy Cycle Configuration |
Config Is Via Addressed Reg |
Yes |
No |
Yes |
|
Address Of Config Reg |
0x300 |
0x00 |
0x15 |
|
|
CMD To Read Config Reg |
0x71 |
0x00 |
0x01 |
|
|
CMD To Write To Config Reg |
0x72 |
0x00 |
1 |
|
|
Register Data |
Data Shift Bits |
0 |
0 |
8 |
|
Data Binary Mask |
0x07 |
0x00 |
0xFF |
|
|
Data To Be Written |
2 |
0 |
64 |
|
|
STR/DTR Configuration |
Address Of Config Reg |
0x0 |
0x00 |
0x00 |
|
CMD To Read Config Reg |
0x71 |
0x00 |
0x00 |
|
|
CMD To Write To Config Reg |
0x72 |
0x00 |
0x00 |
|
|
Register Data |
Data Shift Bits |
0 |
0 |
0 |
|
Data Binary Mask |
0x03 |
0x00 |
0x00 |
|
|
Data To Be Written |
2 |
0 |
0 |
|
|
JEDEC ID Read Configuration |
Read ID CMD |
0x9F |
0x95 |
0x9F |
|
Number Of Bytes To Read |
3 |
5 |
3 |
|
|
Number Of Dummy Cycles In Quad Mode |
0 |
0 |
0 |
|
|
Number Of Dummy Cycles In Octal Mode |
4 |
0 |
8 |
|
|
Advanced Flash Configuration |
Flash Reset Type |
0x10 |
0x10 |
0x10 |
|
Flash Device Busy Type |
LEGACY POLLING OF SR |
LEGACY POLLING OF SR |
LEGACY POLLING OF SR |
|
|
Write Enable CMD |
0x06 |
0x06 |
0x06 |
|
|
Read Status Register CMD |
0x05 |
0x05 |
0x05 |
|
|
WIP Bit |
0 |
0 |
0 |
|
|
WEL Bit |
1 |
1 |
1 |
|
|
WIP Read CMD (xSPI) |
0x05 |
0x00 |
0x00 |
|
|
WIP Status Reg Addr (xSPI) |
0x0 |
0x00 |
0x00 |
|
|
WIP Bit (xSPI) |
0 |
0 |
0 |
|
|
Chip Erase Command |
0xC7 |
0xC7 |
0xC7 |
|
|
Flash Busy Timeout |
40000000 |
112000000 |
72000000 |
|
|
Page Program Timeout |
512 |
256 |
400 |
|
|
Enable 4 Byte Addressing |
Yes |
Yes |
No |
|
|
Supported Addressing Modes |
2 |
1 |
0 |
|
|
4 Byte Addressing Enable Sequence |
0x20 |
0x85 |
0x00 |
|
|
Command Extension Type |
INVERSE |
NONE |
NONE |
|
|
Input Clock Frequency (Hz) |
166666666 |
166666666 |
133333333 |
|
|
Input Clock Divider |
8 |
8 |
4 |
|
|
Enable DMA |
Yes |
No |
Yes |
|
|
Enable PHY Mode |
Yes |
No |
No |
|
Working Configurations for ISSI Serial NOR Flash Parts
|
|
Flash Part Name |
||||
|
IS25LP256D |
IS25WX512 |
||||
| SoC tested on |
AM243x |
AM275x |
|||
|
Flash Parameters |
QSPI |
OSPI |
|||
|
Serial Flash Configuration |
Flash Type |
Serial NOR Flash |
Serial NOR |
||
|
Flash Name |
IS25LP256D |
IS25WX512 |
|||
|
Protocol |
4D-4D-4D |
8D-8D-8D |
|||
|
Basic Flash Configuration |
Flash Size in Bytes |
33554432 |
67108864 |
||
|
Flash Page Size in Bytes |
256 |
256 |
|||
|
Flash JEDEC Manufacturer ID |
0x9D |
0x9D |
|||
|
Flash JEDEC Device ID |
0x6019 |
0x5B1A |
|||
|
Erase Configurations |
Flash Block Size In Bytes |
65536 |
131072 |
||
|
Flash Sector Size In Bytes |
4096 |
4096 |
|||
|
Block Erase CMD (3B) |
0xD8 |
0xD8 |
|||
|
Block Erase CMD (4B) |
0xD8 |
0xDC |
|||
|
Sector Erase CMD (3B) |
0x20 |
0x20 |
|||
|
Sector Erase CMD (4B) |
0x20 |
0x21 |
|||
|
Protocol Enable Configuration |
Read Command |
0xEB |
0xFD |
||
|
Write/Page Program Command |
0x02 |
0x02 |
|||
|
Mode Clocks (CMD) |
0 |
0 |
|||
|
Mode Clocks (READ) |
2 |
0 |
|||
|
Dummy Clocks (CMD) |
0 |
8 |
|||
|
Dummy Clocks (READ) |
4 |
20 |
|||
|
Quad Enable Type |
2 |
0 |
|||
|
Octal Enable Type |
0 |
0 |
|||
|
QPI Sequence |
0x04 |
0x00 |
|||
|
OPI Sequence |
0x00 |
0x00 |
|||
|
Protocol Configuration |
Config Is Via Addressed Reg |
No |
Yes |
||
|
Address Of Config Reg |
0x00 |
0x00 |
|||
|
CMD To Read Config Reg |
0x00 |
0x85 |
|||
|
CMD To Write To Config Reg |
0x00 |
0x81 |
|||
|
Register Data |
Data Shift Bits |
0 |
0 |
||
|
Data Binary Mask |
0x00 |
0xFF |
|||
|
Data To Be Written |
0 |
231 |
|||
|
Dummy Cycle Configuration |
Config Is Via Addressed Reg |
No |
Yes |
||
|
Address Of Config Reg |
0x00 |
0x01 |
|||
|
CMD To Read Config Reg |
0x00 |
0x85 |
|||
|
CMD To Write To Config Reg |
0x00 |
0x81 |
|||
|
Register Data |
Data Shift Bits |
0 |
0 |
||
|
Data Binary Mask |
0x00 |
0xFF |
|||
|
Data To Be Written |
0 |
20 |
|||
|
STR/DTR Configuration |
Address Of Config Reg |
0x00 |
0x00 |
||
|
CMD To Read Config Reg |
0x00 |
0x85 |
|||
|
CMD To Write To Config Reg |
0x00 |
0x81 |
|||
|
Register Data |
Data Shift Bits |
0 |
0 |
||
|
Data Binary Mask |
0x00 |
0xFF |
|||
|
Data To Be Written |
0 |
231 |
|||
|
JEDEC ID Read Configuration |
Read ID CMD |
0x9F |
0x9F |
||
|
Number Of Bytes To Read |
5 |
5 |
|||
|
Number Of Dummy Cycles In Quad Mode |
0 |
0 |
|||
|
Number Of Dummy Cycles In Octal Mode |
0 |
8 |
|||
|
Advanced Flash Configuration |
Flash Reset Type |
0x30 |
0x30 |
||
|
Flash Device Busy Type |
1 |
FLAG SR BIT 7 |
|||
|
Write Enable CMD |
0x06 |
0x06 |
|||
|
Read Status Register CMD |
0x05 |
0x05 |
|||
|
WIP Bit |
0 |
0 |
|||
|
WEL Bit |
1 |
1 |
|||
|
WIP Read CMD (xSPI) |
0x00 |
0x00 |
|||
|
WIP Status Reg Addr (xSPI) |
0x00 |
0x00 |
|||
|
WIP Bit (xSPI) |
0 |
0 |
|||
|
Chip Erase Command |
0xC7 |
0xC7 |
|||
|
Flash Busy Timeout |
60000000 |
256000000 |
|||
|
Page Program Timeout |
200 |
512 |
|||
|
Enable 4 Byte Addressing |
Yes |
Yes |
|||
|
Supported Addressing Modes |
0 |
1 |
|||
|
4 Byte Addressing Enable Sequence |
0xA9 |
0 |
|||
|
Command Extension Type |
NONE |
REPEAT |
|||
|
Input Clock Frequency (Hz) |
166666666 |
200000000 |
|||
|
Input Clock Divider |
8 |
2 |
|||
|
Enable DMA |
No |
Yes |
|||
|
Enable PHY Mode |
No |
Yes |
|||
|
|
|
Patch: https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/6318.diff_5F00_phy.patch |
|||
Working Configurations for GigaDevice Serial NOR Flash Parts
|
|
Flash Part Name |
||||
|
GD25B64C |
|||||
| SoC tested on |
AM273x |
||||
|
Flash Parameters |
QSPI |
||||
|
Serial Flash Configuration |
Flash Type |
Serial NOR |
|||
|
Flash Name |
GD25B64C |
||||
|
Protocol |
1S-1S-4S |
||||
|
Basic Flash Configuration |
Flash Size in Bytes |
8388608 |
|||
|
Flash Page Size in Bytes |
256 |
||||
|
Flash JEDEC Manufacturer ID |
0xC8 |
||||
|
Flash JEDEC Device ID |
0x4017 |
||||
|
Erase Configurations |
Flash Block Size In Bytes |
65536 |
|||
|
Flash Sector Size In Bytes |
4096 |
||||
|
Block Erase CMD (3B) |
0xD8 |
||||
|
Block Erase CMD (4B) |
0x00 |
||||
|
Sector Erase CMD (3B) |
0x20 |
||||
|
Sector Erase CMD (4B) |
0x00 |
||||
|
Protocol Enable Configuration |
Read Command |
0x6B |
|||
|
Write/Page Program Command |
0x02 |
||||
|
Mode Clocks (CMD) |
0 |
||||
|
Mode Clocks (READ) |
0 |
||||
|
Dummy Clocks (CMD) |
0 |
||||
|
Dummy Clocks (READ) |
8 |
||||
|
Quad Enable Type |
1 |
||||
|
Octal Enable Type |
0 |
||||
|
QPI Sequence |
0x00 |
||||
|
OPI Sequence |
0x00 |
||||
|
Protocol Configuration |
Config Is Via Addressed Reg |
No |
|||
|
Address Of Config Reg |
0x00 |
||||
|
CMD To Read Config Reg |
0x00 |
||||
|
CMD To Write To Config Reg |
0x00 |
||||
|
Register Data |
Data Shift Bits |
0 |
|||
|
Data Binary Mask |
0x00 |
||||
|
Data To Be Written |
0 |
||||
|
Dummy Cycle Configuration |
Config Is Via Addressed Reg |
No |
|||
|
Address Of Config Reg |
0x00 |
||||
|
CMD To Read Config Reg |
0x00 |
||||
|
CMD To Write To Config Reg |
0x00 |
||||
|
Register Data |
Data Shift Bits |
0 |
|||
|
Data Binary Mask |
0x00 |
||||
|
Data To Be Written |
0 |
||||
|
STR/DTR Configuration |
Address Of Config Reg |
0x00 |
|||
|
CMD To Read Config Reg |
0x00 |
||||
|
CMD To Write To Config Reg |
0x00 |
||||
|
Register Data |
Data Shift Bits |
0 |
|||
|
Data Binary Mask |
0x00 |
||||
|
Data To Be Written |
0 |
||||
|
JEDEC ID Read Configuration |
Read ID CMD |
0x00 |
|||
|
Number Of Bytes To Read |
0 |
||||
|
Number Of Dummy Cycles In Quad Mode |
0 |
||||
|
Number Of Dummy Cycles In Octal Mode |
0 |
||||
|
Advanced Flash Configuration |
Flash Reset Type |
0x10 |
|||
|
Flash Device Busy Type |
0 |
||||
|
Write Enable CMD |
0x06 |
||||
|
Read Status Register CMD |
0x05 |
||||
|
WIP Bit |
0 |
||||
|
WEL Bit |
1 |
||||
|
WIP Read CMD (xSPI) |
0x00 |
||||
|
WIP Status Reg Addr (xSPI) |
0x00 |
||||
|
WIP Bit (xSPI) |
0 |
||||
|
Chip Erase Command |
0xC7 |
||||
|
Flash Busy Timeout |
6000000 |
||||
|
Page Program Timeout |
4000 |
||||
|
Enable 4 Byte Addressing |
No |
||||
|
Supported Addressing Modes |
0 |
||||
|
4 Byte Addressing Enable Sequence |
0x00 |
||||
|
Command Extension Type |
NONE |
||||
|
Input Clock Frequency (Hz) |
66666666 |
||||
|
Input Clock Divider |
0 |
||||
|
Enable DMA |
No |
||||
|
Enable PHY Mode |
No |
||||
Working Configurations for Renesas Serial NOR Flash Parts
|
|
Flash Part Name |
||||
|
AT25SF64 |
|||||
| SoC tested on |
AM243x |
||||
|
Flash Parameters |
QSPI |
||||
|
Serial Flash Configuration |
Flash Type |
Serial NOR |
|||
|
Flash Name |
AT25SF64 |
||||
|
Protocol |
1S-1S-4S |
||||
|
Basic Flash Configuration |
Flash Size in Bytes |
8388608 |
|||
|
Flash Page Size in Bytes |
256 |
||||
|
Flash JEDEC Manufacturer ID |
0x1F |
||||
|
Flash JEDEC Device ID |
0x8801 |
||||
|
Erase Configurations |
Flash Block Size In Bytes |
65536 |
|||
|
Flash Sector Size In Bytes |
4096 |
||||
|
Block Erase CMD (3B) |
0xD8 |
||||
|
Block Erase CMD (4B) |
0xD8 |
||||
|
Sector Erase CMD (3B) |
0x20 |
||||
|
Sector Erase CMD (4B) |
0x20 |
||||
|
Protocol Enable Configuration |
Read Command |
0x6B |
|||
|
Write/Page Program Command |
0x02 |
||||
|
Mode Clocks (CMD) |
0 |
||||
|
Mode Clocks (READ) |
0 |
||||
|
Dummy Clocks (CMD) |
0 |
||||
|
Dummy Clocks (READ) |
8 |
||||
|
Quad Enable Type |
6 |
||||
|
Octal Enable Type |
0 |
||||
|
QPI Sequence |
0x00 |
||||
|
OPI Sequence |
0x00 |
||||
|
Protocol Configuration |
Config Is Via Addressed Reg |
No |
|||
|
Address Of Config Reg |
0x00 |
||||
|
CMD To Read Config Reg |
0x00 |
||||
|
CMD To Write To Config Reg |
0x00 |
||||
|
Register Data |
Data Shift Bits |
0 |
|||
|
Data Binary Mask |
0x00 |
||||
|
Data To Be Written |
0 |
||||
|
Dummy Cycle Configuration |
Config Is Via Addressed Reg |
No |
|||
|
Address Of Config Reg |
0x00 |
||||
|
CMD To Read Config Reg |
0x00 |
||||
|
CMD To Write To Config Reg |
0x00 |
||||
|
Register Data |
Data Shift Bits |
0 |
|||
|
Data Binary Mask |
0x00 |
||||
|
Data To Be Written |
0 |
||||
|
STR/DTR Configuration |
Address Of Config Reg |
0x00 |
|||
|
CMD To Read Config Reg |
0x00 |
||||
|
CMD To Write To Config Reg |
0x00 |
||||
|
Register Data |
Data Shift Bits |
0 |
|||
|
Data Binary Mask |
0x00 |
||||
|
Data To Be Written |
0 |
||||
|
JEDEC ID Read Configuration |
Read ID CMD |
0x9F |
|||
|
Number Of Bytes To Read |
5 |
||||
|
Number Of Dummy Cycles In Quad Mode |
0 |
||||
|
Number Of Dummy Cycles In Octal Mode |
0 |
||||
|
Advanced Flash Configuration |
Flash Reset Type |
0x10 |
|||
|
Flash Device Busy Type |
1 |
||||
|
Write Enable CMD |
0x06 |
||||
|
Read Status Register CMD |
0x05 |
||||
|
WIP Bit |
0 |
||||
|
WEL Bit |
1 |
||||
|
WIP Read CMD (xSPI) |
0x00 |
||||
|
WIP Status Reg Addr (xSPI) |
0x00 |
||||
|
WIP Bit (xSPI) |
0 |
||||
|
Chip Erase Command |
0xC7 |
||||
|
Flash Busy Timeout |
32000000 |
||||
|
Page Program Timeout |
448 |
||||
|
Enable 4 Byte Addressing |
No |
||||
|
Supported Addressing Modes |
0 |
||||
|
4 Byte Addressing Enable Sequence |
0x00 |
||||
|
Command Extension Type |
REPEAT |
||||
|
Input Clock Frequency (Hz) |
133333333 |
||||
|
Input Clock Divider |
4 |
||||
|
Enable DMA |
No |
||||
|
Enable PHY Mode |
No |
||||
Working Configurations for GigaDevice Serial NAND Flash Parts
|
Flash Part Name |
||||
|
GD5F2GM7UE |
||||
| SoC tested on |
AM62Px |
|||
|
Flash Parameters |
SPI |
|||
|
Serial Flash Configuration |
Flash Type |
Serial Nand Flash |
||
|
Flash Name |
GD5F2GM7UE |
|||
|
Protocol |
1S-1S-1S |
|||
|
Basic Flash Configuration |
Flash Size in Bytes |
268435456 |
||
|
Flash Page Size in Bytes |
2048 |
|||
|
Flash JEDEC Manufacturer ID |
0xC8 |
|||
|
Flash JEDEC Device ID |
0x0092 |
|||
|
Page Load Command |
0x13 |
|||
|
Page Program Command |
0x10 |
|||
|
Erase Configurations |
Flash Block Size In Bytes |
131072 |
||
|
Block Erase CMD |
0xD8 |
|||
|
Protocol Enable Configuration |
Read Command |
0x03 |
||
|
Write/Page Program Command |
0x02 |
|||
|
Dummy Clocks (CMD) |
4 |
|||
|
Dummy Clocks (READ) |
8 |
|||
|
Protocol Configuration |
Config Is Via Addressed Reg |
No |
||
|
Address Of Config Reg |
0x00 |
|||
|
CMD To Read Config Reg |
0x00 |
|||
|
CMD To Write To Config Reg |
0x00 |
|||
|
Register Data |
Data Shift Bits |
0 |
||
|
Data Binary Mask |
0x00 |
|||
|
Data To Be Written |
0 |
|||
|
Dummy Cycle Configuration |
Config Is Via Addressed Reg |
No |
||
|
Address Of Config Reg |
0x00 |
|||
|
CMD To Read Config Reg |
0x00 |
|||
|
CMD To Write To Config Reg |
0x00 |
|||
|
Register Data |
Data Shift Bits |
0 |
||
|
Data Binary Mask |
0x00 |
|||
|
Data To Be Written |
0 |
|||
|
JEDEC ID Read Configuration |
Read ID CMD |
0x9F |
||
|
Number Of Bytes To Read |
2 |
|||
|
Advanced Flash Configuration |
Flash Reset Type |
0x10 |
||
|
Write Enable CMD |
0x06 |
|||
|
Read Status Register CMD |
0x0F |
|||
|
Write Status Register CMD |
0x1F |
|||
|
WIP Status Reg Addr |
0xC0 |
|||
|
WIP Bit |
0 |
|||
|
WIP Read CMD (xSPI) |
0x0F |
|||
|
WIP Status Reg Addr (xSPI) |
0x000000C0 |
|||
|
WIP Read Status Dummy Cycle (xSPI) |
8 |
|||
|
Flash Busy Timeout |
256000000 |
|||
|
Page Program Timeout |
600 |
|||
|
Program Status Register Address |
0xC0 |
|||
|
Program Status Register Addr (xSPI) |
0x000000C0 |
|||
|
Program Status Bit Position |
3 |
|||
|
Erase Status Register Address |
0xC0 |
|||
|
Erase Status Register Address (xSPI) |
0x000000C0 |
|||
|
Erase Status Bit Position |
2 |
|||
|
Write Protection Status Reg Address |
0xA0 |
|||
|
Write Protection Status Mask |
255 |
|||
|
Command Extension Type |
NONE |
|||
|
Input Clock Frequency (Hz) |
100000000 |
|||
|
Input Clock Divider |
4 |
|||
|
Enable DMA |
Yes |
|||
|
Enable PHY Mode |
No |
|||
