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How do the data pass through the internal ports and buses in C6670?

challenger002
Intellectual 690 points

How do the data pass through the internal ports and buses in C6670?

I understood each the data path as follows.

For the load /store instructions by CorePac0.

1. CorePac1 L2:

   CorePac0 MDMA - MSMC CorePac0 Slave Port - MSMC System Master Port - TeraNet CPU/2 - Bridges - TeraNet CPU/3 - CorePac1 SDMA -CorePac1 L2

2. MSMC SRAM:

   CorePac0 MDMA - MSMC CorePac0 Slave Port - MSMC SRAM

3. DDR3:

   CorePac0 MDMA - MSMC CorePac0 Slave Port - MSMC EMIF Master Port - DDR3

For the transfers by system masters except CorePac.

1. CorePac0 L2 and CorePac1 L2:

   CorePac0 L2 - CorePac0 SDMA - TeraNet CPU/3 - CorePac1 SDMA -CorePac1 L2

2. CorePac0 L2 and MSMC SRAM:

   CorePac0 L2 - CorePac0 SDMA - TeraNet CPU/3 - Bridges - TeraNet CPU/2 - MSMC SMS - MSMC SRAM

3. CorePac0 L2 and DDR3:

   CorePac0 L2 - CorePac0 SDMA - TeraNet CPU/3 - Bridges - TeraNet CPU/2 - MSMC SES - MSMC EMIF Master Port - DDR3

Are these right?

Is the MSMC CorePac Slave Port used other than the load /store instructions?

Best regards,

Daisuke

  • 0
    TI__Intellectual 2415 points

    Hi Daisuke,

    Yes you understanding is correct. All the data paths mentioned above are correct.

    No. The MSMC CorePac Slave Port is used only by the CorePAC MDMA transactions (which include load /store instructions).

  • 0 in reply to Karthik Ramana Sankar
    Intellectual 830 points

    Thanks for a very interesting thread.

    I am interested on the memory read and write performance from Core 0 to the L2SRAM (used purely as SRAM) in Core 1, in the case where the data is not in the cache of Core 0 nor in the cache of Core 1.

    App Note SPRABK5 Fig 1 is helpful (as are SPRUGW7A Fig 2-1 and SPRUGW0B Fig 1-1), but Table 4 (and 5) in SPRABK5 do not list this case.

    I note that Table 4 lists the read performance of MSMC RAM (SL2) miss in both L1 cache and Prefetch with Victim as 20.1 (single read) and 11.6 (burst read).

    I'm interested in similar DSP Stall figures for access from Core 0 to the SRAM in Core 1.

    Regards, Jonathan

     

  • 0 in reply to Jonathan White
    TI__Intellectual 2415 points

    Hi Jonathan,

    We did not measure DSP stall figures for Core to Core transfers. The data path for Core to Core transfers is very long and is given below:

    CorePac0 MDMA - MSMC CorePac0 Slave Port - MSMC System Master Port - TeraNet CPU/2 - Bridges - TeraNet CPU/3 - CorePac1 SDMA -CorePac1 L2

    Hence, the DSP stall figures will be on the higher side.

  • 0 in reply to Karthik Ramana Sankar
    Intellectual 690 points

    Hi Karthik

    Thank you for a reply.

    > No. The MSMC CorePac Slave Port is used only by the CorePAC MDMA transactions (which include load /store instructions).

    As for the CorePAC MDMA transactions;

    Do the transactions occur only by L2 cash controler?

    What do the transactions include?
    Do the transactions include only load /store instructions?
    Do the transactions include others (e.g. IDMA)?

    Best regards,

    Daisuke

  • 0 in reply to Karthik Ramana Sankar
    Intellectual 690 points

    Hi Karthik,

    Are there more than two data path between the CPU/3 teranet and the CPU/2 teranet?

    Best regards,

    Daisuke

  • 0 in reply to challenger002
    TI__Intellectual 2415 points

    Hi Daisuke,

    C66x CorePAC MDMA transactions include the following:

    1) load/store CPU instructions, which involve reading/writing to MSMC or DDR3 memory locations (non-cached or cache miss @ L1 or L2)

    2) SW initiated cache coherency (using Cache CSL APIs) between MSMC/DDR3 memory and L1 or L2 cache.

    The MDMA transactions do not include IDMA transactions. The IDMA transactions are used for the following:

    1) Data transfers internal to the C66x CorePAC

    2) C66x Writing/Reading from the MMRs on the CFG bus. However, CFG to CFG transfers are not supported.

    For more details about MDMA or IDMA, please refer to C66x CorePAC users guide (SPRUGW0B).

    To answer your second question:

    There are multiple bridges between CPU/2 and CPU/3 TeraNet. For details about the exact number of bridges, please refer to the "System Interconnect" section of your part number's Data manual. The reason for having multiple bridges between CPU/2 and CPU/3 TeraNet, is to provide Parallel data paths for multiple masters on CPU/2 TeraNet to communicate with multiple CPU/3 slaves and vice versa. However, a single master on CPU/2 TeraNet will not have multiple parallel paths to a particular slave on CPU/3 TeraNet. The same explanation is true for CPU/3 TeraNet Master --> CPU/2 TeraNet Slave.

  • 0 in reply to Karthik Ramana Sankar
    Intellectual 690 points

    Hi Karthik,

    Thank you for a reply.

    I have the issue about the memory throughput as the following link describes it.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/169406.aspx

    However, I seem to be able to solve the issue by your help.

    Can I get your help again?

    Best regards,

    Daisuke