PLL and PSC numbers not necessarily consistent?

Hi,

It seems that there is no fixed relationship between the PLL 0/1 source of an on-chip peripheral and its PSC domain. Although for many peripherals the numbers of PLL and PSC are consistent, there are also many exceptions:

I get confused by these when debugging DDR2 self-refresh and find that:

1. Figure 7-3: VCLK is from PLL0_SYSCLK2(/2)
2. Table 9-2: that DDR2/mDDR belongs to PSC1

and a more careful comparison led to the table above. So can we say that PLL and PSC numbers are separate? I found some support for this:

SPRUH77A p.182, 9.2 Power Domain and Module Topology said:

There are a few modules/peripherals on the device that do not have an LPSC assigned to them. These modules do not have their module reset/clocks controlled by the PSC module. The decision to assign an LPSC to a module on a device is primarily based on whether or not disabling the clocks to a module will result in significant power savings.

This makes me feel like that the design of PSC is more like hindsight. When the designer looks at the various peripherals, they may say “well, let’s add clock-gating ability so the user can save more power when this module is off”, hence comes various PSCs. The peripherals using more than one clock sources such as DDR2/mDDR (both from PLL0_SYSCLK2 and PLL1_SYSCLK1), it is completely up to the chip designer to decide which PSC should the module be assigned to. If we regard it like a pipeline in which clock signal flowing from PLL0 or PLL1 can be gated by the valve-like PSC, then it will seem less surprising why module using PLL0 can be gated by PSC1, and vice versa, because PLL and PSC are simply different phase of the pipeline / different stages.

Could someone clarify on this?

Paul