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L138 EDMA3: Will TC0 or TC1 be used?

Paul Singh
Expert 2750 points

Hi,

The EDMA3 controller 0 of L138 has two associated transfer controllers (TC0, TC1), so how do we know which TC will be used to execute a certain transfer request?

In “18.2.13.3 Dequeue Priority” of SPRUH77,

The priority of the associated transfer request (TR) is further mitigated by which event queue is being used for event submission (dictated by DMAQNUMn and QDMAQNUM). For submission of a TR to the transfer controller, events need to be dequeued from the event queues. A lower numbered queue has a higher dequeuing priority then a higher numbered queue. For example, if there are events in Q0 and Q1 and the respective transfer controllers (TC0 and TC1) are ready to receive the next TR from the EDMA3CC, then the transfer requests associated with events in Q0 will get submitted to TC0 prior to any transfer requests associated with events in Q1 getting submitted to TC1.

My understand from this paragraph is that this seems to suggest:

(1)  The EDMA3 logic sorts the event queues first, with lower event number having higher dequeuing priority.

(2)  The EDMA3 then pops out events. At this moment there could be at most two TCs free for the case of EDMA3_0, so

  1. If only one TC free, then that PC is used.
  2. If two TCs are free, then the one with smaller index number (TC0 < TC1) is used.

Is the actual rule SPRUH77 tried to tell us?

 

Paul

  • 0
    TI__Guru** 116170 points

    Yes, your understanding is correct.

  • 0
    Expert 1040 points

    Paul Singh said:

    (1)  The EDMA3 logic sorts the event queues first, with lower event number having higher dequeuing priority.

    (2)  The EDMA3 then pops out events. At this moment there could be at most two TCs free for the case of EDMA3_0, so

    1. If only one TC free, then that PC is used.
    2. If two TCs are free, then the one with smaller index number (TC0 < TC1) is used.

    To me, it sounds like you're saying that an event is popped from Q0 (if not empty) else from Q1 (if not empty), and then that event is serviced by the highest priority TC that is not busy.   Rahul agreed with you, but the documentation clearly states that events in Q0 always get serviced by TC0 and events in Q1 always get serviced by TC1.

    So perhaps what you meant to say is when both Q0 and Q1 have events, if TC0 is not busy, then Q0's event is popped and dispatched to TC0, but if TC0 is busy, no event from Q0 is popped.  Instead the event in Q1, the lower priority queue, gets popped and dispatched to TC1.

    Rahul, can you please clarify?

    Thanks,
    Elron

  • 0 in reply to Elron A Yellin
    TI__Guru* 83815 points

    Elron A Yellin said:

    So perhaps what you meant to say is when both Q0 and Q1 have events, if TC0 is not busy, then Q0's event is popped and dispatched to TC0, but if TC0 is busy, no event from Q0 is popped.  Instead the event in Q1, the lower priority queue, gets popped and dispatched to TC1.

    Rahul, can you please clarify?

    Rahul might be tied up, but yes the above statement is correct too.

    If there are events in both queues and both TCs are free, Q0 gets dequeque prior to Q1. If TC0 is occupied and Q1 has an event to dequeue to TC1 , even if there is an event in Q0, the event from Q1 will dequeue to TC1.

  • 0 in reply to Mukul Bhatnagar
    Expert 1040 points

    Mukul Bhatnagar said:

    Rahul might be tied up, but yes the above statement is correct too.

    Thanks.  I take that to mean what I wrote is correct, and despite your "too", that the statement of the original post is incorrect (since they are contradictory).