SPI boot mode - C6670 - Chip Select 1

Aymeric,

I think this is in your custom board. We haven't tried anything but CS0. But it should work for all the Chip Select. I am not sure I understand the probe result. What you mean by CS) active. The boot strap is used to select the chip select that is connected to your flash. In the EVM we have the CS0 connected to the flash and CS1 connected to FPGA. In your setup does CS1 is connected to the flash?

Thanks,

Arun.

Arun

You have understood correctly. There are 2 chips select, one is connected to a NOR Flash and another is connected to another device.

When we use CCS, initialize the board using a gel file and access the flash device using our drivers (platform lib with adaptation), we use CS1. We can Read Write and do all we need.

Our problem is that on boot, using the settings described above, CS1 is never getting active (low), therefore the C6670 does not read the flash device.

Aymeric

Aymeric,

What is the pin mode you are selecting? you need to select 4 pin mode.

Thanks,

Arun.

hello,ArunMani

I have two questions about BCP .

firstly , I don't know how to understand the Output Data of RM module in BCP? why it is not match the format of 36.212 in 3GPP?

Secondly ,I want check the SSL module with the Output data of MOD,Whether it is feasible?

Thank you

Arun,

Sorry that I have 2 posts in parallel but I see them as 2 different issues. The first one is creating the boot table inside the SPI and the second (this one) is what the HW engineer believes to be a problem in the RBL.Our board uses the same NOR flash as the EVM, it is on CS1 rather than 0 but that is about where the differences stop.

To answer your question, our bootstrap set up is as follow:

My devstat = 0x3150D. (we tried also 3140D,3160D and 3170D which are all the combination for CS)

And here is the description according to section 2.4.2.6 of the data manual SPRS689D p34

Little endian, SPI parameter table index 0, chip select (0b00 - 0b01 - 0b10 - 0b11) (we need CS1 but the manual is confusing), 24 bit address, 4 pins (0 for bit 10 which according to manual is 4 pin mode used - there is no 5 pin mode with SPI), mode1for the CLK pol/phase.

Using this setting (whatever CS bits are), CS1 is never active and we do not see any activity on the CLK signal or SPII or SPIO)

Our HW engineer found the following post:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/165943/773551.aspx#773551

I will get back to you after investigating a bit more this new information

Aymeric

Arun,

I completed the investigation with my colleague and here is what we see:

On boot (with devstat - 0x3150d where CS=0b01), we can see that the DSP tries to access a device. There is activity on the clock signal and on the data, however we never see the CS being latch.

We compares the SPI registers from boot (RBL configuration) to what they are when we can read and write the NOR flash. We think the RBL is not configuring the SPI pin control register properly. At boot, we see 0x01010E01 when it should be 0x01010E03 or 02.

Then SPI default chip select register settings is used to control the CS. This register is configured correctly in the RBL.

Aymeric

Aymeric,

Can you try 5 pin mode. The devstat should be 0x31D0D.

Thanks,

Arun.

Aymeric,

Any update on this issue?

Thanks,

Arun.