Other Parts Discussed in Thread: OMAPL138
Hi,
I'm trying to configure the L138 PLL from the DSP at startup. I've attached the code below. After configuring it, it never seems to change frequency. Specifically the EMIF clock. I'm trying to set it to 100MHz but it stays at 25MHz after I've configured it.
I've even checked using a gel file from one of the forums used for diagnostic. It says the PLL is setup correctly and should be set to 100MHz. Do you see anything I may have done wrong.
My configuration code is now based on the "C6000 DSP+ARM Processor Technical Reference Manual" instructions with some additions from a gel file that was provided to me.
Thanks for your help.
Regards,
James McNEill
#define PLL_LOCK_TIME_CNT 2400
#define PLL_STABILIZATION_TIME 2000
#define PLL_RESET_TIME_CNT 200
void Initialize(void)
{
GIO_Attrs gioAttrs = GIO_ATTRS;
Int32 result;
Int UartStatus = 0;
Uint32 cntDACmem=0;
Uint32 temp;
Uint32 temparray[2048];
Uint32 FPGA_Ver_Major, FPGA_Ver_Minor, FPGA_Ver_Build;
// Gpio_Params gpioParams=Gpio_PARAMS;
//-------------------------------------------------
// CONFIGURE PIN MUXES
//-------------------------------------------------
//-- Write Unlock code to the Kick Registers
SYSCONFIG0->KICK0R = KICK0R_Unlock;
SYSCONFIG0->KICK1R = KICK1R_Unlock;
//-- Setup Pin Muxes
//-- Setup EMFA, UART2, MMCSD0, Inerrupt GPIOs
SYSCONFIG0->PINMUX0 = PINMUX0_VALUE;
SYSCONFIG0->PINMUX1 = PINMUX1_VALUE;
SYSCONFIG0->PINMUX2 = PINMUX2_VALUE;
SYSCONFIG0->PINMUX3 = PINMUX3_VALUE;
SYSCONFIG0->PINMUX4 = PINMUX4_VALUE;
SYSCONFIG0->PINMUX5 = PINMUX5_VALUE;
SYSCONFIG0->PINMUX6 = PINMUX6_VALUE;
SYSCONFIG0->PINMUX7 = PINMUX7_VALUE;
SYSCONFIG0->PINMUX8 = PINMUX8_VALUE;
SYSCONFIG0->PINMUX9 = PINMUX9_VALUE;
SYSCONFIG0->PINMUX10 = PINMUX10_VALUE;
SYSCONFIG0->PINMUX11 = PINMUX11_VALUE;
SYSCONFIG0->PINMUX12 = PINMUX12_VALUE;
SYSCONFIG0->PINMUX13 = PINMUX13_VALUE;
SYSCONFIG0->PINMUX14 = PINMUX14_VALUE;
SYSCONFIG0->PINMUX15 = PINMUX15_VALUE;
SYSCONFIG0->PINMUX16 = PINMUX16_VALUE;
SYSCONFIG0->PINMUX17 = PINMUX17_VALUE;
SYSCONFIG0->PINMUX18 = PINMUX18_VALUE;
SYSCONFIG0->PINMUX19 = PINMUX19_VALUE;
//--------------------------------------
// Configure the PLLs
//--------------------------------------
printf("SETTING UP THE PLLs");
//-- Clear the PLL register lock
//SYSCONFIG0->CFGCHIP0 &= ~(0x00000010);
SYSCONFIG0->CFGCHIP0 &= ~CSL_SYSCFG_CFGCHIP0_PLL_MASTER_LOCK_MASK;
SYSCONFIG0->CFGCHIP3 &= ~CSL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_MASK;
//-- Program the PLL mode bit to internal Oscillator.
PLL_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_CLKMODE_MASK;
//-- Clear the PLLENSRC bit
PLL_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLENSRC_MASK;
//-- Set External source to internal oscillator
PLL_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_EXTCLKSRC_MASK;
//-- Set the PLLEN to '0'
PLL_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLEN_MASK;
//-- Wait 5 cycles for PLLEN to take affect
for(temp=0; temp<4; temp++) {;}
//-- Clear the PLL reset bit
PLL_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLRST_MASK;
//-- Disable the PLL output
PLL_regs->PLLCTL |= CSL_PLLC_PLLCTL_PLLDIS_MASK;
//-- Clear the PLL power down bit
PLL_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLPWRDN_MASK;
//-- Enable the PLL output
PLL_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLDIS_MASK;
//-- Wait for the PLL stabilisation time
for(temp=0; temp<PLL_STABILIZATION_TIME; temp++) {;}
//-- Program PLLM
PLL_regs->PLLM = CSL_PLLC_PLLM_PLLM_MASK & 24;
//-- Make sure PREDIV is enabled
PLL_regs->PREDIV |= CSL_PLLC_PREDIV_PREDEN_MASK;
//-- Disable POSTDIV
// PLL_regs->POSTDIV |= CSL_PLLC_POSTDIV_POSTDEN_MASK;
PLL_regs->POSTDIV = CSL_PLLC_POSTDIV_POSTDEN_MASK | 1;
//-- Wait for GOSTAT to clear
while ( (PLL_regs->PLLSTAT & 0x1) == 1 ){}
//-- Program the PLLDIVx Registers
PLL_regs->PLLDIV1 = (0 & CSL_PLLC_PLLDIV1_RATIO_MASK) | CSL_PLLC_PLLDIV1_D1EN_MASK;
PLL_regs->PLLDIV2 = (1 & CSL_PLLC_PLLDIV2_RATIO_MASK) | CSL_PLLC_PLLDIV2_D2EN_MASK;
PLL_regs->PLLDIV3 = (2 & CSL_PLLC_PLLDIV3_RATIO_MASK) | CSL_PLLC_PLLDIV3_D3EN_MASK;
PLL_regs->PLLDIV4 = (3 & CSL_PLLC_PLLDIV4_RATIO_MASK) | CSL_PLLC_PLLDIV4_D4EN_MASK;
PLL_regs->PLLDIV6 = (0 & CSL_PLLC_PLLDIV6_RATIO_MASK) | CSL_PLLC_PLLDIV6_D6EN_MASK;
PLL_regs->PLLDIV7 = (5 & CSL_PLLC_PLLDIV7_RATIO_MASK) | CSL_PLLC_PLLDIV7_D7EN_MASK;
//-- Wait for GOSTAT to clear
while ( (PLL_regs->PLLSTAT & 0x1) == 1 ){}
//-- Set GPSET bit to '1'
PLL_regs->PLLCTL |= CSL_PLLC_PLLCMD_GOSET_MASK;
//-- Wait for GOSTAT to clear
while ( (PLL_regs->PLLSTAT & 0x1) == 1 ){}
//-- Wait for PLL to reset properly
for(temp=0; temp<PLL_RESET_TIME_CNT; temp++) {;}
//-- set the PLL reset bit
PLL_regs->PLLCTL |= CSL_PLLC_PLLCTL_PLLRST_MASK;
//-- Wait for the PLL to LOCK
for(temp=0; temp<PLL_LOCK_TIME_CNT; temp++) {;}
//-- Set the PLLEN to '1'
PLL_regs->PLLCTL |= CSL_PLLC_PLLCTL_PLLEN_MASK;
SYSCONFIG0->CFGCHIP3 &= ~CSL_SYSCFG_CFGCHIP3_EMA_CLKSRC_MASK;
//-- Set the PLL register lock
//SYSCONFIG0->CFGCHIP0 |= (0x1 << 4) & 0x00000010;
SYSCONFIG0->CFGCHIP0 |= CSL_SYSCFG_CFGCHIP0_PLL_MASTER_LOCK_MASK;
SYSCONFIG0->CFGCHIP3 |= CSL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_MASK;
//
// END PLL SETUP
//------------------------------------------
//----------------------------------
//-- Setup FPGA Memory Space.
//----------------------------------
//EMIFA_regs->CE2CFG = 0x8244125;
EMIFA_regs->CE2CFG = 0x83441A9;
printf("SETUP THE EMIF MEMORY SPACE\n");
}
