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Confirm CLKOUT pin behavior of C553x

Kaka
Guru 24520 points
Other Parts Discussed in Thread: PCM1681, CDCS503-Q1, CDCE913

Hi community member,

Please let me confirm the following question.

[Question.1]

Regarding to the TRM of C553x, CLKOUT pin can generate the signal of PLLOUT by changing the register of CCSSR.

However, I could not see the PLLOUT even though I changed the register from mode11 to mode 2.

Can this pin generate the PLLOUT signal?

[Question.2]

Regarding to the register map of CCSSR, there are the same descriptions (i.e. CLKOUT pin outputs System PLL output clock, PLLOUT.) on this table.

Is there any differences for those descriptions? (i.e. is there any difference between mode2 and mode 4 and so on?)

Note: Mode2 means that the value of SRC is "2h". Mode4 also means that the value of SRC is "4h".

If you have any questions, please let me know.

Best regards,

Kaka

  • 0
    TI__Mastermind 23785 points

    Kaka-san,

    What is the setting of CLKOUT enable pin in CPU ST3_55? That bit needs to be set to enable for CLKOUT after bootloader finishes.

    "The CLKOUT pin's output driver is enabled/disabled through the CLKOFF bit of the CPU ST3_55 register.

    At hardware reset, CLKOFF is cleared to 0 so that the clock is visible for debug purposes. But within the

    bootloader romcode, CLKOFF is set to 1 to conserve power. After the bootloader finishes, the customer

    application code is free to re-enable CLKOUT. For more information on the ST3_55 register, see the

    following reference guides: TMS320C55x 3.0 CPU Reference Guide (SWPU073)"

    There is no difference for mode 2h and mode 4h settings.

    Regards.

     

     

  • 0 in reply to Steve Tsang
    Guru 24520 points

    Hi Steve, 

    Thank you for your response.

    THe register of CLKOFF in ST3_55 was enabled when I confirmed the behavior  of this pin.

    So, I could observe the signal of SYSCLK at CLKOUT pin.

    My concern is that the output signal did not change from SYSCLK to PLLCLK even though the register of CCSSR was changed from default value to 2h.

    Best regards, 

    Kaka

  • 0 in reply to Kaka
    TI__Mastermind 23785 points

    Kaka-san,

    C5535 is same silicon as C5515. I have just confirmed the function with a C5515 EVM scoping the CLKOUT pin. After CCS is up, I changed the ST3 to enable CLKOUT. Then changed 0x1C24 to 1h to observe CLKOUT as high; then changed 0x1C24 to 2h and observing the different PLL programming via my GEL file.

    Do you have a C5515 EVM to check it out?

    Regards.

  • 0 in reply to Steve Tsang
    Guru 24520 points

    Hi Steve,

    Thank you for your experiments.

    Yes,  I have this board and I had confirmed the correct behavior in case of using the SRC register values of "1h",  "3h" and  7h.

    However,  when this register values were "0h" ,"2h", "4h","6h", the CLKOUT pin generated the SYSCLK.

    Regarding to TRM, if use those values, the CLKOUT pin will be expected to generate the signal of PLLOUT.

    So, would you please double check this behavior in your environment?

    Best regards,

    Kaka

  • 0 in reply to Kaka
    TI__Mastermind 23785 points

    Kaka-san,

    I tried 0h, 2h, 4h, 6h, 8h, Ah, Ch and Eh, it is actually SYSCLK of before the peripheral clock gating via SYSCLKDIS bit in PCGCR1. You can refer to Figure 1-6. 0Bh is the SYSCLK after the clock gating and it is off when SYSCLKDIS is enabled while the other selections will still have a clock. Please note CLKOUT is for debug purpose only and is not recommended as clock source to other devices. I will update TRM as such.

    Regards.

  • 0 in reply to Steve Tsang
    TI__Mastermind 23785 points

    Kaka-san,

    Further clarification. I tested with the SYSCLKSEL bit in CCR2, bit 0 of 1C1Fh. The PLLOUT of 0h, 2h, 4h, 6h, 8h, Ah, Ch and Eh is actually the System Clock Generator LS output. It is still active on CLKOUT after SYSCLKDIS bit in PCGCR1 is enabled, bit 15 of 1C02h. Bh settng with send SYSCLK to CLKOUT; it can further programmed by PLL Divider, 1C23h, SYSCLKSEL bit and SYSCLKDIS bit.

    1C02h bit 15, SYSCLKDIS in PCGCR1               1C1Fh bit 0, SYSCLKSEL in CCR2                1C23h         1C24h        CLKOUT

    0                                                                             0                                                                       0                 B                 32kHz

    0                                                                             0                                                                       003             B                 32kHz

    0                                                                            0                                                                        203             B                 32kHz

    0                                                                            1                                                                        0                 B                 PLL w/o DIV

    0                                                                            1                                                                        003             B                 PLL w/o DIV

    0                                                                            1                                                                        203             B                 PLL w DIV

    0                                                                             0                                                                       0                 2                 PLL w/o DIV

    0                                                                             0                                                                       003             2                 PLL w/o DIV

    0                                                                            0                                                                        203             2                 PLL w DIV

    0                                                                            1                                                                        0                 2                 PLL w/o DIV

    0                                                                            1                                                                        003             2                 PLL w/o DIV

    0                                                                            1                                                                        203             2                 PLL w DIV

    Regards.

  • 0 in reply to Steve Tsang
    Guru 24520 points

    Hi Steve,

    Thank you for your confirmation.

    Please let me confirm my understanding of CLKOUT behavior just in case.

    [My understanding]

    If 1C24h is "2h"(PLLOUT), the CLKOUT pin will generate the output signal of Clock Generate which is described in Figure 1-7 on TRM.

    * Just in case, I attached this figure to this POST. And I pointed the output signal at red circle on this figure.

    Is my understanding correct?

    Best regards,

    Kaka

  • 0 in reply to Kaka
    TI__Mastermind 23785 points

    Kaka-san,

    Yes. It is the output of the LS.

    Regards.

  • 0 in reply to Steve Tsang
    Guru 24520 points

    Hi Steve,

    Thank you for confirming my concern.  I can clear my concern by your answer.

    Beet regards,

    Kaka

  • 0 in reply to Steve Tsang
    Prodigy 250 points

    Steve Tsang said:
    Please note CLKOUT is for debug purpose only and is not recommended as clock source to other devices. I will update TRM as such.

    In my C5535 application, I'm using CLKOUT for exactly this - it feeds a CPLD which generates read timing for an external ADC, and formats the ADC data to feed it into an I2S port on the DSP. It's a useful feature to have - I wouldn't write it off as a "debug purposes only" pin.

  • 0 in reply to gmarsh
    TI__Mastermind 23785 points

    I would like to point out that we do not guarantee CLKOUT be glitch free in all circumstances. Thus, we stated in data sheet that CLKOUT pin is for debug purpose.

    Regards.

  • 0 in reply to Steve Tsang
    Prodigy 250 points

    Could you elaborate?

    My application can tolerate glitches when switching the CLKOUT source, or when enabling/disabling the output in the STx register - my CPLD is held in reset during that time.

    Thanks!

  • 0 in reply to gmarsh
    TI__Mastermind 23785 points

    We have not characterize all conditions. And changing clock sources is one of the condition that would create glatches.

    Regards.

  • 0 in reply to Steve Tsang
    Prodigy 140 points

    Is clockout pin give output in LVCMOS ? ..would this clock become glitch free ,if i put cdcs503-q1 clock buffer in path between C5535(DSP) And PCM1681(DAC) ?

    For synchronize purpose...Can i use the RTC CLOCKOUT pin As a LVCMOS source for another clock multiplier ...?

  • 0 in reply to CHIRAG PATEL1
    TI__Mastermind 23785 points

    CLKOUT is specified in data manual that it is for debug purposes only. We do not guarantee it is glitch free. We know it would create glitches when changing clock sources.

    As for the RTC_CLKOUT, it can be used as a 32kHz clock. Please refer to Electrical Characteristics table for their voltage and current specifications. Both are output/tri-state pins.

    Hope this help.

    Regards.

  • 0 in reply to Steve Tsang
    Prodigy 140 points

    sir,   i know that RTC_CLCKOUT is tri-state , 32KHz And 5ma output pi,...but in datasheet there is no any mention about the output types of this pin ,...is it LVCMOS or TTL type? 

    And sir what about clockout pin use about some of seconds ,with keeping stable  CLK source ,..And then after give this output to clockbuffer to drive another system.?

  • 0 in reply to CHIRAG PATEL1
    TI__Mastermind 23785 points

    The whole device is in LVCMOS. Clock buffer cannot prevent glitches. You can use CLKOUT as you see fit in your application.

    Regards.

  • 0 in reply to Steve Tsang
    Prodigy 140 points

    Thanx for your clearification ,sir

    ...from this conversation i am decide to use cdce913 clock ,..for whole system.

    worm regards.