DM816x C674x DSP L2 Cache Configuration

Bandeg

Hello:

We are trying to optimally configure the on-chip memory for the DSP.

The memory map for the DM8168 C674x (DSP) indicates that the DSP L2 RAM is 256KB.

It looks like 128K is presently configured as L2 cache (config_1G_256MLinux.bld),
and the remainder is given to the .internalHeap (in BIOS_c6xdsp.cfg)

1. Can we configure to L2mode=256k?

    I tried the following in config_1G_256M, and temporarily moved .internalheap to ddr.

        ["DSP_L2_RAM", {
            comment: "DSP_L2_RAM",
            name: "DSP_L2_RAM",
            base: 0x10800000,
            len: 0x00040000
        }],
    ],
    l1PMode: "32k",
    l1DMode: "32k",
    l2Mode: "256k"

The build gives the following error:

configuring MAIN_APP_c6xdsp.xe674 from package/cfg/MAIN_APP_c6xdsp_pe674.cfg ...
error: ti.platforms.evmTI816X.Platform: "/drive/rdk/ti/DVRRDK_03.00.01.03/ti_tools/xdc/xdctools_3_23_03_53/packages/xdc/platform/Utils.xs", line 365: ti.platforms.evmTI816X.Platform.Instance#0/customMemoryMap/'DSP_L2_RAM' : Memory object DSP_L2_RAM does not fit into any physical memory bank.
js: "/drive/rdk/ti/DVRRDK_03.00.01.03/ti_tools/xdc/xdctools_3_23_03_53/packages/xdc/cfg/Main.xs", line 149: Error: Configuration failed!
gmake: *** [package/cfg/MAIN_APP_c6xdsp_pe674.xdl] Error 1
js: "/drive/rdk/ti/DVRRDK_03.00.01.03/ti_tools/xdc/xdctools_3_23_03_53/packages/xdc/tools/Cmdr.xs", line 51: Error: xdc.tools.configuro: configuration failed due to earlier errors (status = 2); 'linker.cmd' deleted.
make[3]: *** [xdc_configuro] Error 1
make[3]: Leaving directory `/drive/rel-4.3/lic/ti8168/DVRRDK_03.00/dvr_rdk/mcfw/src_bios6/main_app'
make[2]: *** [apps] Error 2
make[2]: Leaving directory `/drive/rel-4.3/lic/ti8168/DVRRDK_03.00/dvr_rdk/mcfw/src_bios6'
make[1]: *** [dvr_rdk_bios6] Error 2

Are there more changes that we need to do for this experiment?

2. If we can use L2mode=256K, can we redirect the internalHeap, and other critical DSP sections to other 'resident' memory like OCMC SRAM ?
Alternatively, can we configure the entire L2 cache itself to other memory regions (like OCMC SRAM)?

Regards,

--B

over 12 years ago

0 Badri Narayanan over 12 years ago

TI__Guru 59700 points

Bandeg said:
1. Can we configure to L2mode=256k?

- The chnges to configure L2 cache to 256K is correct. Pls share the changes done to move the interalHeap to DDR ? This error is because xdc platform defintiion does validation of memory regions and finds L2SAM section wrondly placed. Did you also modify the platform defintion to remove the

["DSP_L2_RAM", {
            comment: "DSP_L2_RAM",
            name: "DSP_L2_RAM",
            base: 0x10800000,
            len: 0x00040000
        }],

section ?

Bandeg said:
If we can use L2mode=256K, can we redirect the internalHeap, and other critical DSP sections to other 'resident' memory like OCMC SRAM ?
Alternatively, can we configure the entire L2 cache itself to other memory regions (like OCMC SRAM)?

OCMC is already used fully for placing critical M3 code in DVR RDK. You could use some portion of OCMC (maybe 32K) but will be unable to get 128K free.EVen if you use OCMC it would be 6x more access time compared to using GEM L2. Are you seeing significant improvement by setting DSP L2 cache to 256K ?

It is not possible to configure L2 cache to any other memory regions.

0 Bandeg over 12 years ago in reply to Badri Narayanan

Expert 1140 points

Thanks, Previously, I didn't remove the DSP_L2_RAM section. Now that I have, it compiles.

Now I have 256K of L2 cache, and I will continue to test.

By increasing the L2 to 256K, all DSP sections are now in DDR3. Are there any critical sections, used by BIOS, etc., that we should reconsider adding back to the L2 SRAM?

.internalHeap contains MAIN_APP_c6x_pe674.oe674, what is this used for and should we leave it where it was in L2 SRAM?

Are there any other "local" memory areas, faster than DDR3 but slower than Cache, that we can use for DSP sections?

Regards,

--B

0 Badri Narayanan over 12 years ago in reply to Bandeg

TI__Guru 59700 points

The L2SRAM is exclusively used for the internal heap. The internal heap L2 SRAM heap (.internalHeap) is used as scratch memory by SWOSD , SCD algorithm.The algorithms DMA line of data to L2 ,do the core kernel operation in L2 and DMA out the updated contents so that the core processing loop is not stalled in DDR access.If you dont use these algorithms in your usecase there will be no impact of moving the internalHeap out of L2.

There is no other fast memory available . Ducati L2 is fully used and so is OCMC.HDVICP SL2 is for exclusive use of HDVICPs.If you have to use OCMC you can move M3 code out of OCMC and use it (provided your usecase is not bottlenecked by M3 Mhz).The 816x data sheet L3 connectivity table mentions OCMC cannot be accessed by c674 MDMA . I need to confirm with experts if this means OCMC cannot be accessed by c674 if it is cached.I will update this post once I get additional info.

0 aa aa1 over 11 years ago in reply to Bandeg

Prodigy 180 points

Hello, I am doing the saming thing with IPNC RDK 3.5

Would tell me how to remove the "DSP_L2_RAM section" in xdc platform define?

Which files should I modify? thanks a lot!

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DM816x C674x DSP L2 Cache Configuration