external event trigger edma fail

Weslly,

Are you using the CSL functions to initialize and operate the EDMA3?

Have you started from a working example for the EDMA?

Most likely, EMRH and SERH are set, and if that is true then no further use of that channel is possible until they are cleared. If I recall correctly, a useful sequence for clearing those is either

1. Repeatedly clear SER/SERH until it returns as 0, then clear EMR/EMRH.

2. Clear SER/SERH four times, then clear EMR/EMRH.

Option 2 is faster because it does not require reads of the SER/SERH registers over the slow Config Bus. I always add code to do option 2 to my initialization sequences.

Regards,
RandyP

Thanks, RandyP,

Yes, I'm using CSL to initial EDMA3 and really started from a CSL example.

Also, the right bit in SERH was set, but i'm sure it's not set ahead of GPIO4 event, i.e., GPIO4 event set both ERH and SERH! Is this abnormal?

Regards,

Weslly

Weslly,

Can you be specific about the CSL example that you started with, please?

The SERH bit being set means that no more events will get through. This is why ERH is set.

If more than one event trigger comes in on the GPIO4 pin to reach the EDMA event inputs, then this can cause too many events if the EDMA has not finished with the first event. You can read about this in the EDMA3 User Guide. Search for SER to see the several places where this register is discussed in the EDMA3 User Guide.

What is connected to your GPIO4 pin to cause the DMA event to be triggered?

Regards,
RandyP

RandyP,

The example i transplanted from was a ping-pong example from CSL lib, called "edma_ping_pong_xfer_reg5".

And GPIO4 is fed by FPGA, actually is a fifo half-full signal, to ask dsp read data from this fifo.

I searched everywhere about SER, seems get no idea. By the way, if i use GPIO4 as an interrupt, and manually trigger EDMA in the interrupt handler, you see, set ESR. Then EDMA works, and in this way, EDMA is connecting to event 5:CSL_EDMA3_CHA_5.

thanks,

Weslly.

Weslly,

With the event-driven method (not CPU-driven), do any data get transferred?

Is the EMRH register set also when you see the SERH register set?

The test using GPIO4 to cause an interrupt is an excellent one, and this confirms that the basic setup of your PARAM is correct. This is very good information.

As a test of the event-driven method, can you clear the EERH register bit so an event in ERH will not cause a DMA transfer? Then run to the point that the EDMA is completely setup and then let the FPGA trigger the GPIO4 pin one time only. Observe the ERH register confirm that it gets set, and observe all of the other registers, like EMRH and SERH to make sure nothing bad has happened yet.

If some error bits are already set, that will suggest one direction to look for problems. If no error bits are set, then you will want to set the EERH bit and see what happens when the event is allowed to progress through the queue'ing process.

Please let us know of your results.

Regards,
RandyP

Hi, RandyP,

No data transferred under event-driven way, i confirmed by chipscope inside FPGA. And that's why i think this event is not pushed into queue to be further served.

EMRH wasn't set.

For the way of testing you provided, seems i did it before, only SERH set, no other error bit. But any way, i will re-do it to confirm and let you guys know. While it may take several days, since i will have a business trip from tomorrow.

thanks,

Weslly

Weslly,

My test recommendation is a slow procedure that will require stepping through or manually setting bits. You had EERH set in your test; I said to clear EERH so the event in ERH will not progress to SERH. Then you can more easily observe what happens immediately after you enable EERH to allow the event through.

In your earlier test, having both SERH and ERH set implies that two event pulses were received into ERH.

Please report the values in the following registers for your GPIO4 DMA channel: DCHMAPn, DMAQNUMn, QUETCMAP, EMRH, CCERR, QSTATn, and CCSTAT. Also, report any other registers in the EDMA that changed from before enabling EERH to after enabling EERH (when ERH is set).

Also include the PARAM contents for your GPIO4 DMA channel and the address of the same.

Regards,
RandyP