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MSP430 SYS/BIOS "coreId" code is Esoteric and Needs Explaining

Fred Rupinski
Prodigy 110 points
Other Parts Discussed in Thread: MSP430F5438A, SYSBIOS

Platform: MS XP SP3, CCS 5.4.0, MSP-EXP430F5438 (MSP430F5438A chip installed) and the MSP-FET430UIF (USB)

I created a new CCS SYS/BIOS project that has the following code in the template that was created automatically:

*  ======== Idle.c ========
 *  Implementation of Idle_loop.
 */

#include <xdc/std.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/hal/Core.h>
#include <ti/sysbios/hal/Hwi.h>

#include "package/internal/Idle.xdc.h"

/*
 *  ======== Idle_loop ========
 */
Void Idle_loop(UArg arg1, UArg arg2)
{
    while (TRUE) {
        Idle_run();
    }
}

/*
 *  ======== Idle_run ========
 */
Void Idle_run()
{
    Int i;
    UInt coreId;

    if (BIOS_smpEnabled == TRUE) {
        coreId = Core_getId();
    }
    else {
        coreId = 0;
    }

    for (i = 0; i < Idle_funcList.length; i++) {
        if (Idle_coreList.elem[i] == coreId) {
            Idle_funcList.elem[i]();
        }
    }
}

I have no notion of why "coreId, Core_getId(), Idle_funcList.length, Idle_coreList.elem[i] ,or Idle_funcList.elem[i]();" are incluuded in an MSP430 single core project, or what this code is supposed to do. Can someone explain?

  • 0
    TI__Mastermind 30830 points

    For some targets and devices with symmetric CPU cores sharing a common memory map, SYS/BIOS can be configured to work in Symmetric Multi-Processor (SMP) mode. In SMP mode, a common code image is executed by all the cores in the system. In order for core-specific behavior to be supported, a 'coreId' unique to each core is used in a few places within SYS/BIOS to allow thread bifurcation.

    In order to use a common C source code base for both non-SMP and SMP modes of operation, there are several places within the SYS/BIOS code where you will see references to BIOS_smpEnabled and 'coreId' that may seem out of place.

    In an SMP system, there is a separate Idle task running on each core, each with its own set of Idle functions to be executed. In order to support this mode of operation, a 'shadow' Idle_coreList[] array to the Idle_funcList[] array is used which defines which core a specific idle function within the Idle_funcList[] is to run on.

    In non-SMP systems such as MSP430s, the shadow array is filled with 0's and a comparison with zero is forced rather than an actual coreId.

    I hope this explanation clears up the confusion.

    Alan

  • 0 in reply to Alan DeMars
    Prodigy 110 points

    Thanks for the explanation. However, this code seems to be unnecessary baggage for single core devices such as MSP430s (unless future multi-core MSP430s are in the works…).

     

    Fred A Rupinski