HS200 tuning flow on U-boot

Hello Sirs,

Have anyone know my question about the MMCHS_DLL Register?

with Best Regards,

ShinFu

shinfu huang said:

Hi Sirs,

I have an TI OMAP 5432 evm board, and i download GLSDK 6_01_00_01 for linux and u-boot source code.

I want to add eMMC HS200 flow in my uboot, but i have some question in CMD21 tuning flow

That is my tuning function. Refer to OMAP5432 RTM  24.5.1.2.4, SD104/HS200 DLL Tuning Procedure.

2627.tuning.txt

I always hang on step 3(MMCHS_DLL[0] all always unlock!!), after i setting MMCHS_AC12[22] ET to 0x1.

By the way, in the step one, the MMCHS_DLL regester value is 0x80000000,

Thanks.

with Best Regards,

ShinFu

Hello ShinFu,

I suggest you to have a look in section 25.4.14 Sampling Clock Tuning in OMAP5 TRM.

The check for states of MMCHS_CAPA2[13] TSDR50 and MMCHS_CAPA2[15:14] RTM are missing
in your tuning.txt. I suggest you to add a check-up of these bits before using SDR104/HS200 or SDR50.

2. The software starts the tuning sequence by setting MMCHS_AC12[22] ET to 1. Then it issues CMD19 for
a SD card or CMD21 for an eMMC device repeatedly until MMCHS_AC12[22] ET is set to 0.
MMCHS_AC12[22] ET is reset when the tuning is complete or when the tuning is not complete within 40
tries. The software may abort this loop if the number of the loops reaches 40 or 150ms timeout occurs. In
this case a fixed sampling clock is used and MMCHS_AC12[23] SCLK_SEL is set to 0. This indicates that
the tuning procedure is failed. When MMCHS_AC12[23] SCLK_SEL is set to 1, this indicates that the
tuning procedure is completed successfully. Once the tuning circuit is reset, it will take time to complete tuning sequence. Therefore, Host Driver should keep this bit to 1 to perform re-tuning sequence to compete re-tuning sequence in a short time.

Best regards,

Yanko

Hi Yanko,

I try to add the check for states of MMCHS_CAPA2[13] TSDR50 and MMCHS_CAPA2[15:14] RTM,

that is all zero for those.

But those just provided for Read, and i don't know the RTM how to use?

Do you have sample code for UHS-1 or HS200 tuning flow?

Thanks.

with Best Regards,

ShinFu

Yanko Todorov-XID said:

Hello ShinFu,

I suggest you to have a look in section 25.4.14 Sampling Clock Tuning in OMAP5 TRM.

The check for states of MMCHS_CAPA2[13] TSDR50 and MMCHS_CAPA2[15:14] RTM are missing
in your tuning.txt. I suggest you to add a check-up of these bits before using SDR104/HS200 or SDR50.

2. The software starts the tuning sequence by setting MMCHS_AC12[22] ET to 1. Then it issues CMD19 for
a SD card or CMD21 for an eMMC device repeatedly until MMCHS_AC12[22] ET is set to 0.
MMCHS_AC12[22] ET is reset when the tuning is complete or when the tuning is not complete within 40
tries. The software may abort this loop if the number of the loops reaches 40 or 150ms timeout occurs. In
this case a fixed sampling clock is used and MMCHS_AC12[23] SCLK_SEL is set to 0. This indicates that
the tuning procedure is failed. When MMCHS_AC12[23] SCLK_SEL is set to 1, this indicates that the
tuning procedure is completed successfully. Once the tuning circuit is reset, it will take time to complete tuning sequence. Therefore, Host Driver should keep this bit to 1 to perform re-tuning sequence to compete re-tuning sequence in a short time.

Best regards,

Yanko

Hi Yanko,

Thank you for your information.

These sample code is different to the suggested tuning procedure in OMAP5 TRM.

Why the software tuning procedure is to set dll register?

/* Start software tuning Procedure */
dll |= DLL_SWT;
OMAP_HSMMC_WRITE(host->base, DLL, dll);

with Best Regards,

ShinFu

Hello ShinFu,

The DLL register must be configured, because this register is used for tuning procedure.

The DLL is not part of the MMC/SDIOi host controller. It is instantiated at top level between the IOs and the host controller. There are two DLLs. One for MMC1 when SDR104 mode is used and one for MMC2 when HS200 mode is used.

The fragment, which you mentioned - /* Start software tuning Procedure */
                                                                       dll |= DLL_SWT;
                                                                       OMAP_HSMMC_WRITE(host->base, DLL, dll);

It sets the Forced fine delay value in bit-field MMCHS_DLL[21:20] FORCE_SR_F.

Best regards,

Yanko

Hi Yanko Todorov-XID,

Thank you, i already can do tuning...in 96MHz

How can I change the source clock from 96MHz to 192 MHz?

Thank you..

with Best Regards,

ShinFu

Hello ShinFu

To change source clock from 96MHz to 192MHz,  select a new clock source for MMC1 or MMC2 by registers in PRCM:

- CM_L3INIT_MMC1_CLKCTRL[24] CLKSEL_SOURCE - 0x1: 192MHz clock derived from DPLL_PER is selected.

- CM_L3INIT_MMC2_CLKCTRL[24] CLKSEL_SOURCE - 0x1: 192MHz clock derived from DPLL_PER is selected

The 192MHz clock is provided from DPLL_PER, and check the status of M2 divider by CM_DIV_M2_DPLL_PER register.

For more information see Figure 3-39. CM_CORE Overview (a) in OMAP5 TRM.

Use the Clock Tree Tool (CTT) OMAP543x Clock Tree Tool (v1.9.0.8) for detailed look on OMAP's clock signals.

Best regards,

Yanko

Hi Yanko,

CM_DIV_M2_DPLL_PER  not be used, so these is default value.

and i have question about CM_L3INIT_MMC1_CLKCTRL/CM_L3INIT_MMC2_CLKCTRL Register

in uboot code :

#define HSMMC_CLKCTRL_CLKSEL_MASK (1<<24)

#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK(1<<25)

/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);

/* Set the correct clock dividers for mmc */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);

is it related with 96MHz to 192MHz?   Why we need to set cm_l3init_hsmmc2_clkctrl[25] = 1?

if i want to change the bit[25] to 0, is it ok?

And what is mean of OPP_NOM?

with Best Regards,

ShinFu 

Hello ShinFu,

is it related with 96MHz to 192MHz?

I think that, if you want to change frequency of MMCs, you must apply the necessary configuration in PRCM registers related with MMC. These are the main ways to enable 192Mhz.

Why we need to set cm_l3init_hsmmc2_clkctrl[25] = 1? if i want to change the bit[25] to 0, is it ok?

 - CM_L3INIT_MMC2_CLKCTRL[2] CLKSEL_DIV - MMC2 clock divide ratio  0x0: MMC2 clock is divided by 1, to be used for  OPP_NOM.  0x1: MMC2 clock is divided by 2.  See the figure:

These registers control the switches, dividers and multiplexors in the figure above.

And what is mean of OPP_NOM? - This is Operating Point corresponds to nominal power mode of the device.

Best regards,

Yanko

hi shinfu,

can you show me your sample code for HS200 tuning? i have the same problem with you.

the setps of HS200 tuning in TRM and sample code in Android are different, I use the sample code in Android ,but always timeout at

err = wait_for_completion_timeout(&host->buf_ready,
     msecs_to_jiffies(5000));

thanks!