cannot configure EDMA3 application registers

Are you trying to use computer to access C6678 EDMA registers via PCIe link please?

Please try to set "MST_PRIV" to 1 in PRIORITY register in C6678 PCIe to set PCIe in Supervisor mode in order to access chip level registers. Please see section 3.1.14 in PCIe user guide for details.

Hi, Steven,

       I not quite sure if I access EDMA registers via PCIe link, I just call API functions(WDC_WriteAddr32()) from Windriver to configure EDMA registers, It's just like I configure PCIe application register(like outbound translate registers).

       I try to set  "MST_PRIV" to 1 in PRIORITY register in C6678 PCIe ,I can write "MST_PRIV" bit to 1 in PRIORITY register correct , but I still cannot write to the registers I memtioned above(list in first post) , I tried to read from these registers , It all comes 0x0;

Mike,

You call API of WinDriver on computer (PC) side and try to setup registers on C6678 DSP side, is it correct?

If your are able to access PCIe application registers, the BAR0 register in C6678 should be setup correctly to accept the packets from PC for the access. Since BAR0 is dedicated to PCIe application registers region in C6678, which BAR are you using for accessing the EDMA registers please? Do you setup that BAR correctly to accept the packets (BARn should match the PCIe addressing of the incoming packets)?

It is interesting that you mentioned you could access PaRAM setup registers but not other EDMA registers. Do they have the same EDMA3 base address? And is the register offset the only difference please?

Please note that some EDMA registers are Read Only (such as IPR) or Write Only(such as ESR). Please double check if you are doing valid access to these registers.

Steven,

About the first question, I think your understanding is correct.

I configure BAR2 to access the EDMA registers.

I pretty sure that they have the same EDMA3 base address(0x02700000), and only the register offset is different. About the PaRAM registers, there is another weird situation: after running my transfer function, lots of the PaRAM registers become 0x0, and only LINK is 0xFFFF.

Mike,

Could you please share your setup on both PC (WinDriver) and 6678 sides please?

For example, if you are trying to write 0x123 to DMAQNUM0 register (0x02700000+0x240) in C6678 from PC (WinDriver), what is outbound PCIe address of this memory write transaction from PC(WinDriver) please?

What are the BAR2 and BAR2 mask registers setup on C6678 to match the incoming PCIe address please?

Do you set BAR2 to be EDMA registers space (such as 0x02700000) for the direct access or do you use the Inbound translation for this access please (set BAR2 to be other address value and wait for inbound translation)?

If you use the inbound translation, do you enable the Inbound translation (IB_XLT_EN bit) in CMD_STATUS register please?

And what are the Inbound translation registers IB_BARn, IB_STARTn_LO,IB_STARTn_HI,IB_OFFSETn setup to translate and forward the PCIe packets from PC to C6678 EDMA3 CC0 registers space (0x02700000) please?

And are you able to use the same configuration setup to access PaRAM registers, such as PaRAM set 0 (0x02700000+0x4000) correctly, but not for DMAQNUM0 please?

For PaRAM value update, please take a look at section "2.3.6 Parameter Set Updates" and section "Linking Transfers" in EDMA user guide. The PaRAM 

The link update occurs after the current PaRAM set event parameters have been exhausted. An event's parameters are exhausted when the EDMA3 channel controller has submitted all the transfers associated with the PaRAM set.

If STATIC bit in OPT is clear and the value of LINK is FFFFh, then a null PaRAM set (with all 0s and LINK set to FFFFh) is written to the current PaRAM set. Similarly, if LINK is set to a value other than FFFFh, then the appropriate PaRAM location pointed to by LINK is copied to the current PaRAM set.

So what you are observing might be expected depends on your linking setup.

Steven,

the following list  the board memory and interrupt information that the driver detected after the EVM plug into pcie slot:

[

Vendor ID: 0x104C, Device ID: 0xB005
Location: Bus 0x1, Slot 0x0, Function 0x0
Memory range [BAR 0]: base 0xFE400000, size 0x100000
Memory range [BAR 1]: base 0xD1400000, size 0x80000
Memory range [BAR 2]: base 0xD1000000, size 0x400000
Memory range [BAR 3]: base 0xD0000000, size 0x1000000
Memory range [BAR 4]: base 0xD1490000, size 0x1000
Memory range [BAR 5]: base 0xD1480000, size 0x10000
Interrupt: IRQ 11
Interrupt Options (supported interrupts):
Message-Signaled Interrupt (MSI)
Level-Sensitive Interrupt

] 

Basically, my transfer function code is re-edit function HAL_WriteDMA() in pciedemo.c located in C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader

For example,in pciedemo.c, when write to DMAQNUM0 register, it's code says "myIowrite32(0x0, pReg + DMAQNUM0/4); " however my transfer function code replace the "myIowrite32(0x0, pReg + DMAQNUM0/4) " with "WDC_WriteAddr32(hDev, 2 , DMAQNUM0 ,0x0) " .all other DSP registers setting is the same with this example.

The setting of inbound translation registers:(most same with pciedemo.c, only some details are different)

[

/* Configure IB_BAR0 to BAR0 for PCIE registers; Configure IB_BAR1 to BAR1 for LL2 for core 0
Configure IB_BAR2 to BAR2 for EDMA; Configure IB_BAR3 to BAR3 for DDR */
for (i = 0; i < 4; i++) {
WDC_WriteAddr32(hDev, 0, IB_BAR(i), i);
WDC_WriteAddr32(hDev, 0, IB_START_LO(i), barStart[i]);//barStart[i] is list above(like 0xFE400000.etc)
WDC_WriteAddr32(hDev, 0, IB_START_HI(i), 0);
}
WDC_WriteAddr32(hDev, 0, IB_OFFSET(0), PCIE_BASE_ADDRESS);
WDC_WriteAddr32(hDev, 0, IB_OFFSET(1), LL2_START);
WDC_WriteAddr32(hDev, 0, IB_OFFSET(2), EDMA_TPCC0_BASE_ADDRESS);//little difference to pciedemo.c
WDC_WriteAddr32(hDev, 0, IB_OFFSET(3), DDR_START);

]

about the two questions :"Do you set BAR2 to be EDMA registers space (such as 0x02700000) for the direct access or do you use the Inbound translation for this access please (set BAR2 to be other address value and wait for inbound translation)?" and "And are you able to use the same configuration setup to access PaRAM registers, such as PaRAM set 0 (0x02700000+0x4000) correctly, but not for DMAQNUM0 please?"

for the first one, I thougt is the inbound translation for the access,and the second one's answer is yes.

Also I have a question for you:should I set registers BARn and BARn mask? I thought the IBL has setted already.

Mike,

I think BARn mask has been setup in IBL/RBL and BARn is set during bus enumeration by host.So you may not need to modify them.

It looks like the setup you have is correct. And you do not need to divide register address by 4 (DMAQNUM0/4) in WDC_WriteAddr32()  to get the correct index to access the register, is it correct?

If so, when you try to set 0x123 in DMAQNUM0 (WDC_WriteAddr32(hDev, 2 , DMAQNUM0 ,0x123)?), what is the value you read on C66x side (such as 0x02700000+0x240 in CCS memory view) please?

And are you able to access L2 and DDR3 regions correctly using BAR1 and BAR3 please?

If so, are you able to access EDMA registers if you map EDMA base address to BAR1 or BAR3 please?

WDC_WriteAddr32(hDev, 0, IB_OFFSET(1), EDMA_TPCC0_BASE_ADDRESS);

or
WDC_WriteAddr32(hDev, 0, IB_OFFSET(3), EDMA_TPCC0_BASE_ADDRESS);

Steven,

As parameter in WDC_WriteAddr32() is offset address, so you do not need to divide by 4.

The register DMAQNUM0 can write and read correct. so if you write 0x123, you will read 0x123.

I am able to access L2 and DDR3 regions correctly using BAR1 and BAR3.

and I tried to access EDMA registers by mapping the EDMA base address to BAR3, the same problem happened.

Also,here is another situation: I can transfer the data correctly inside DSP(like from 0x10800000 to 0x80000000) with same code(there is a parameter in the transfer function decide which kind transfer you want, inside DSP or between GPP and DSP). but when transfer between GPP and DSP, the data in outbound region0 can transfer to desitination correctly, but the data in outbound region0 is not the same with the data in GPP.