DM814x IBIS models for McASP pins

Hi Steve,

Stephen Turner said:

The datasheet tells you how you can enable/disable pull up/down, but there is no mention of selecting a "fast" or "slow" speed.  How is this selected?.

The reason that we have several models is due to configurability of the IO in different modes. If one is seeing some slews (faster) then this should be the behavior of the IO. Selection of one mode or another has to be checked with the device limits for that interface and what is the correct bit setting. The slew rate of the IO is a function of frequency.

The particular model to select depends entirely on how software has the particular pin configured.

Please refer also to the below links:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/155132/614508.aspx#614508

http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/66225/244692.aspx#244692

http://processors.wiki.ti.com/index.php/How_to_use_the_AM335x_IBIS_Models

http://www.ti.com.cn/cn/lit/an/spra839a/spra839a.pdf

Regards,
Pavel

Hi Pavel

Thanks for your reply.

>>The particular model to select depends entirely on how software has the particular pin configured.

Understood. However its not obvious (to me at least) how you would select a FAST vs SLOW pin configuration for the McASP pin - what register allows you to do this?. 

Unless , when the pin is configured as a GPIO, it automatically uses SLOW and when configured as McASP it uses FAST.  Can you confirm this?.

regards

Steve

Steve,

Stephen Turner said:

Understood. However its not obvious (to me at least) how you would select a FAST vs SLOW pin configuration for the McASP pin - what register allows you to do this?

It is the PINCNTLx[19] SLEWCTRL bit, it selects between Faster and Slower Slew rate, 0x0 for fast, 0x1 for slow. The reset value is pad/pin dependent. But as you can notice, this PINCNTLx[19] is documented as reserved in the DM814x datasheet and TRM. It is because of the following SiliconErrata advisory:

http://www.ti.com/lit/er/sprz343c/sprz343c.pdf

Advisory 2.1.88  Control Module, Pin Configuration (PINCNTLx): ROM Modifies Bit 19

Details: Bit 19 within each PINCNTL[270:1] register is a RESERVED bit which should not be
            modified by any software during device operation. The reset value is specified to ensure
            datasheet minimum and maximum I/O timings are satisfied across all of the various
            functions mapped to the corresponding pin. The ROM bootloader initialization incorrectly
            modifies bit 19 for some of the PINCNTLx registers. Table 4 and Table 5 identify the
            PINCNTLx registers, per boot mode, affected by the ROM bootloader incorrectly
            modifying bit 19 from its default value.

Note: The ROM bootloader will attempt successive boot methods if a previous boot
         mode fails. One or more boot modes may apply depending on the configured
         BTMODE[4:0] pins.

Note: In addition to the ROM bootloader software, the following TI software packages
         may potentially modify bit 19 of the PINCNTLx registers. If any of the following TI
         software packages are used, care should be taken to properly reset bit 19 to the default
         value during device operation:
         • U-BOOT
         • LINUX Kernel (board init files, video drivers)
         • HDVPSS Firmware

Workaround:
To prevent potential datasheet I/O timing violations, software should set bit 19 for all
PINCNTLx registers to the reset value defined in the device-specific data manual.
Software should also ensure that bit 19 of all PINCNTLx registers is not modified during
device operation.

Stephen Turner said:

Unless , when the pin is configured as a GPIO, it automatically uses SLOW and when configured as McASP it uses FAST.  Can you confirm this?.

No, the pin SLOW/FAST usage depends on the reset value of PINCNTLx[19] bit.

Best regards,
Pavel