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C674x maximum SPI master rate

Jason Fritz
Prodigy 20 points


Hi,

I'm trying to find out if I can use a C674x to ingest data from an ADC that outputs on a SPI bus at 100 MHz. The processor would be the SPI Master. Can any of these DSPs (or others) handle this rate or is an FPGA my only option? I'm trying to find a processor <2 W.

Thanks!

  • 0
    TI__Expert 4760 points

    Hi Jason,

    The maximum SPI clock frequency supported by C674x device is 50MHz or 3P whichever is greater

    P=SYSCLK2 period

    Please refer the datasheet for more details page no 165 General Timing Requirements for SPI0 Master Modes.

    Regards

    Antony

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