Question about C6670 PCIe configuration

Those address 0x7000_0000 and 0x9000_0000 are PCIE addresses across the PCIE bus. Then the PCIE inbound translation registers convert this address into a DSP internal address.

Attached is a screenshot of the related PCIE registers in the MCSDK test example to help you understand:

0x2180_0200 region is for OB

0x2180_0300 region is for IB

0x2180_1010 region is for BAR

For example, in the EP side, OB is 0x9000_0001, it generates PCIE address 0x9000_0000 alike crossing the PCIE bus to RC. At the RC, this address matches BAR1 (0x2180_1014) range so it is accepted. Then RC's IB translates this into LL2: incoming PCIE address - 0x9000_0000 + 0x1082_2100.

Similarly, in RC side,   OB is 0x7000_0001, it generates PCIE address 0x7000_0000 alike crossing the PCIE bus to EP. At the EP, this address matches BAR1 (0x2180_1014) range so it is accepted. Then EP's IB translates this into LL2: incoming PCIE address - 0x7000_0000 + 0x1082_2100.

You can change above 0x7000_0000 and 0x9000_0000 to something else.

For Keystone I device, the PCIE memory address is fixed of 256 MB starting at 0x6000_0000. 

For the above MCSDK code, when EP write something to 0x6000_1234, it generates a write with PCIE address 0x9000_1234, it lands to RC's side LL2 0x9000_1234 - 0x9000_0000 + 0x1082_2100 = 0x1082_3334.

Hope this help.

Regards, Eric

 3060.PCIE_translation.docx