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PCIE address translation

murad qahwash
Genius 3770 points
Hello all, Can some one explain to me (in simple English) how the Inbound/Outbound translation works!...I read both the "PCIe_sprugs6c" and "PCIe Use Cases for KeyStone Devices_sprabk8" but still not clear how it works...specifically, if you can explain the numbers used in the sample example "pcie_sample.c" located at: C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\pcie\example\sample what the numbers: PCIE_OB_LO_ADDR_M = 0x70000000, PCIE_IB_LO_ADDR_M=0x90000000 means and why the bars and regions selected as givien in the example? what is the source and destination address for Inbound/Outbound? PS: I see hoe the .CMD maps the dstBuf to L2SRAM and how to map this to global L2 for CoreX Regards, Murad
  • 0 in reply to lding
    Genius 3770 points
    Thank you Eric for the great explanation! what limits and relation among Regions/BARs/and type 0 and type 1 Please. EP: BAR0-5, RC: BAR0-1; Regions: OB = 32, IB = 4 (DLL code shows only 8 Regions) Regards, Murad
  • 0 in reply to murad qahwash
    Genius 3770 points
    Hi Eric, Things start to make sense, but Example 2 (SPRABK8) confused me again...how "the data packets with PCIe address 0x12345678_70000000~0x12345678_70BFFFFF (12 MB) will be transferred to the internal DDR location as 0x8912_5678~0x89D2_5677" In example 1 they used dstAddr in the calculations, in Example 2, they used srcAddr???? Regards, Murad
  • 0 in reply to murad qahwash
    TI__Guru* 95265 points

    The first is OB write, you have something in your LL2 and write to 0x6001_5678, now what is the PCIE address across the bus? It is 0x9001_5678 via OB Translation.

    The second is OB read, you want to read something into your DDR3. So the DST is your DDR3 and SRC is 0x6xxx_xxxx alike. The address on the PCIE bus is of 0x12345678_70000000. The OB regions 18/19 translates 0x6980_0000 and 0x6990_0000 into those 12 MB region.

    Regards, Eric

  • 0 in reply to lding
    Genius 3770 points
    Thank you Eric, Sorry for this bottleneck but: I understood the Write case and for OB, PCIESS uses 5 bits of the "Internal Address" to select the "Region". My confusion now in the OB Read...In this case "Reading" is NOT considered "Inbound"!?. So what [27:23] bits are used to select the Region? what is the relation between 0x8912_5678 and 0x12345678? is it an EDMA thing (not familiar with EDMA) Regards, Murad
  • 0 in reply to murad qahwash
    TI__Guru* 95265 points

    Outbound transfer means the local device initiates the transactions to write to or read from the external device. The CPU or the device-level EDMA is used for outbound data transfer. The PCIe module does not have built-in EDMA.

    Inbound transfer means the external device initiates the transactions to write to or read from the local device. The PCIe module has a master port to transfer the data to or from the device memory; no CPU or EDMA is needed for inbound transfer in the local device.

    But there is no limit for which two regions are chosen. For example, if we choose Region 18 and Region 19 for the translation.

    Bits [27:23] = 18 = 10010b --> 0x6900_0000;

    Bits [27:23] = 19 = 10011b --> 0x6980_0000;

    0x8912_5678 is the destination of the movement. 0x1234_5678 is the external address HI 32-bit. The point is, from your local PCIE device, you are moving data between 0x8912_5678 and 0x6900_0000 for 12MB range, this move can use EDMA or CPU. The OB translates the 0x6900_0000 into PCIE bus address of 0x1234_5678_7000_0000.  

    Regards, Eric

     

  • 0 in reply to lding
    Genius 3770 points
    Thank you Eric for your help and patient :-). Finally, I got it! Regards, Murad