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CDCE clock in C667x

alex martin1
Prodigy 190 points
Other Parts Discussed in Thread: CDCE62005

Hi every body;

I have some question about CDCE62005 used in c6678 EVM : 

1- What is the advantage of using CDCE in EVM board while there are some disadvantages such as very high temperature and high power consumption?

2- Is it important to use accurate low jitter clock for DSP? For example, can we use a 50 ppm clock for C66xx?

3- Is it necessary that all input clock of DSP to be synchronous to each other?

4- Could it possible to provide DSP’s LVDS clocks from LVDS output of a FPGA?

Thanks,

Alex

 

  • 0
    TI__Mastermind 42545 points

    Hi Alex,

     1- The EVM required that all the clocks inputs for the C6678 be present for testing. Most customers do not need all the clocks since they may not be utilizing all the interfaces in the part. The CDCE62005 was abled to generate the clocks we needed in the space available and it's a TI part. We are TI, after all. 

    2- The jitter requirements vary depending on the clock. While the CORECLK and PASSCLK inputs can tolerate a more generic clock with less stringent jitter requirements, the SerDes clocks need to meet the jitter mask for their particular interface. The CDCE62005 was able to provide a clock that met the jitter mask for all the SerDes interfaces on the board. 

    3- It is not necessary that the clocks of the DSP be synchronous. 

    4- The LVDS output of an FPGA would probably meet the requirements for CORECLK, PASSCLK and possible DDRCLK. You would have to check the phase jitter performance against the jitter masks in the KeyStone Hardware Design Guide to determine whether it was sufficient for those interfaces.

    Regards, Bill