DM814xevm M3 core UART with DMA

Jam,

How big is the first transfer? Have you checked whether the transfer complete interrupt occurred from EDMA?

Hi,

1.I am running core m3 at 100MHz. When I set serial baud rate 4800Mhz,Things works fine but problem occurs at 9600 and above baud rate.I am running core A8 at 600MHz and no problem at all baud rate.

2. I am receiving 1st completion interrupt ,but strange thing is I receive another interrupt before 2nd transfer but no error  and interrupt is set in IPR and error register.

3.I do not receive transfer completion interrupt for 2nd transfer.

4. I have checked it with different bytes from 10 to 100 bytes.

Sorry this problem also exist for A8 core also if frequency of this core is set to 100MHz..

Does DMA does not work at this lower frequency of CPU?

Thanks

Jam,

Have you checked what it the UART controller frequency, when you made all these clock changes? Also have you checked the clock of EDMA?

Hi Renjith,

UART controller and EDMA3 are using default settings.So UART is running at 48MHz and EDMA3 is running on 220MHz.

Thanks

Jam,

How did you change ARM's clock frequency? Are you sure that you are not changing anything except ARM's frequency?

Hi,

I am not changing any thing else except core frequency as DPLLs is separate  PLL for Cortex A8

Thanks.

Hi,

Ok, lets try the following.

1. Can you confirm that UART is working properly at A8 @ 100MHz without EDMA? 

2. Can you check whether interrupts are cleared after the first transfer?

3. Can you probe the UART lines to see whether how many bytes are really transferred? 

4. If nothing works out, can you dump the EDMA registers for the channel used and compare with working case when A8 is clocked higher?

1. UART works at 100MHz with out DMA

2. Interrupts are cleared.

3. 1st transaction occurs only  then no transaction occurs.

4. For 100MHz case with DMA

In 1st transaction I see an event  is set in Secondary Event Register. But I am clearing this in my code.

I receive an extra interrupt after 1st completion interrupt but no interrupt is set in IPR.I am not understanding why this interrupt is being received.No error in error registers.

Renjith,

Have you tried EDMA at lower frequency of CPU?

Thanks

I've not tried this use case here. But I'm wondering why it stops working. One reason for second interrupt is that since the CPU is running slow, the handler is triggered slowly, before it clears or disable global interrupt, you are getting recursive interrupts. You can experiment with this by delaying the handler more. 

Probably, since you are handling the interrupt twice, may be the next transfer would have also got aborted. Its like a nested interrupt handler of the same interrupt. What do you think?

Sounds like this could be due to errata advisory 3.0.76 ?  The slower IRQ handling could result in the FIFO filling up and:

If a FIFO full condition is allowed, it is possible that an extra dma_request pulse can occur resulting in a TX sync error.

Hi,

Thanks but this also does not solve the problem