I've got a project setup with the C6670 eval board which sends data via ethernet to/from external PC applications. The PHY chip on the eval board is hard wired to SGMII1 (switch port 2). Using my code, I can successfully send data to and from the DSP.
Moving over to our own board, we are using a different PHY model and connecting it to SGMII0 (switch port 1). Looking at all the status registers it looks like all links (SGMII, Copper, etc) have been established and locked. I am able to send data in and have it received by the DSP. However, anything that the DSP transmits never makes it out of the switch subsystem based on the statistics on port 0 and port 1 / 2.
My switch configuration is as follows:
CSL_CPSW_3GF_enablePort0();
stats.poAStatEnable = 1;
stats.poBStatEnable = 1;
stats.p1StatEnable = 1;
stats.p2StatEnable = 1;
CSL_CPSW_3GF_setPortStatsEnbaleReg(&stats);
CSL_CPSW_3GF_enableAle();
CSL_CPSW_3GF_getAlePoerControlReg(0,&control);
control.portState = ALE_PORTSTATE_FORWARD;
CSL_CPSW_3GF_setAlePoerControlReg(0,&control);
CSL_CPSW_3GF_getAlePoerControlReg(0,&control);
control.portState = ALE_PORTSTATE_FORWARD;
CSL_CPSW_3GF_setAlePoerControlReg(0,&control);
CSL_CPSW_3GF_getAlePoerControlReg(0,&control);
control.portState = ALE_PORTSTATE_FORWARD;
CSL_CPSW_3GF_setAlePoerControlReg(0,&control);
Any suggestions as to which registers I should look into?
Thanks,
Raj
