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some issue about multi core boot by IBL on c6678l evm

Woo Alex
Prodigy 40 points

hello, veryone


I want to run a single image .out on all 8 cores of C6678, which is booted by IBL in the IIC EEPROM from nor flash.


The nor flash was programmed with my own .out by norwriter ultility. The .out is all implemented in L2 SRAM, as my .cmd file is like below:

/*
 *  Linker command file
 *
 */

-c
-heap  0x8000
-stack 0x10000

/* Memory Map 1 - the default */
MEMORY
{
    /* Local L2, 0.5~1MB*/
    VECTORS:     o = 0x00800000  l = 0x0020000
    LL2_RW_DATA:     o = 0x00820000  l = 0x00060000

    /* CORE0 L2, 0.5~1MB*/
    CORE0_VECTORS:     o = 0x10800000  l = 0x00000200
    CORE0_LL2_RW_DATA:     o = 0x10800200  l = 0x0003FE00

    /* CORE1 L2, 0.5~1MB*/
    CORE1_VECTORS:     o = 0x11800000  l = 0x00000200
    CORE1_LL2_RW_DATA:     o = 0x11800200  l = 0x0003FE00

    /* CORE2 L2, 0.5~1MB*/
    CORE2_VECTORS:     o = 0x12800000  l = 0x00000200
    CORE2_LL2_RW_DATA:     o = 0x12800200  l = 0x0003FE00

    /* CORE3 L2, 0.5~1MB*/
    CORE3_VECTORS:     o = 0x13800000  l = 0x00000200
    CORE3_LL2_RW_DATA:     o = 0x13800200  l = 0x0003FE00

    /* Shared L2 2~4MB*/
    SL2_SRAM:          o = 0x0C000000  l = 0x00400000
/*
    SL2_CORE0:         o = 0x0C000000  l = 0x00050000
    SL2_CORE1:         o = 0x0C050000  l = 0x00050000
    SL2_CORE2:         o = 0x0C100000  l = 0x00050000
    SL2_CORE3:         o = 0x0C150000  l = 0x00050000
*/
    /* External DDR3, upto 2GB per core */
    DDR3_CODE:     o = 0x80000000  l = 0x01000000   /*set memory protection attribitue as execution only*/
    DDR3_R_DATA:     o = 0x81000000  l = 0x01000000      /*set memory protection attribitue as read only*/
    DDR3_RW_DATA:     o = 0x82000000  l = 0x06000000   /*set memory protection attribitue as read/write*/
}

SECTIONS
{
    vecs               >    LL2_RW_DATA
    .csl_vect:      >    LL2_RW_DATA

    .cinit          >    LL2_RW_DATA
    .const          >    LL2_RW_DATA
    .switch         >    LL2_RW_DATA

    .text:          >    LL2_RW_DATA
    .boot           >    LL2_RW_DATA
    .data           >    LL2_RW_DATA
    .fardata        >    LL2_RW_DATA
    .neardata       >    LL2_RW_DATA
    .rodata         >    LL2_RW_DATA
    .stack          >    LL2_RW_DATA
    .bss            >    LL2_RW_DATA
    .far            >    LL2_RW_DATA
    .cio            >    LL2_RW_DATA
    .sysmem         >    LL2_RW_DATA
    platform_lib    >    LL2_RW_DATA
}

In my .out, core0 initialize the platform first, and then copy all  the 512KB content of core0's local L2 SRAM to core1's local L2 SRAM After this done, modify the boot magic address of core1. At last send IPC to core1.


As my understanding of the multi core boot, core1 will run normally with the code of core1's local L2 SRAM, which copied by core0 from core0's local L2 SRAM. But core1 doesn't. As i want core1 toggle the led2 on the board when it's just always lighting.

I want to konw is there anything mistake i have taken with the process?

Many thanks!

  • 0
    Prodigy 40 points

    the boot magic address of core1 has been set as “&_c_int00”.


    I‘m not sure whether this can run normal. When core1 enter from the _c_int00 linked from RTS lib, will it run the "idle" again?

  • 0 in reply to Woo Alex
    Prodigy 40 points

    I have also set the boot magic address of core1 as the address of "main", but core1 doesn't run as my expect either.

    what should I try next?

    I really expect some help.

  • 0 in reply to Woo Alex
    TI__Guru** 116170 points

    Hi Woo Alex,

    Have you looked at the multicore boot example srioboot_helloworld that is provided inside MCSDK under the path

    \tools\boot_loader\examples\srio\srioboot_helloworld\src\srioboot_helloworld.c

    This is similar to your usecase wherein the same code runs on the all cores but core0 wakes up the secondary cores by unlocking the KICK registers and then writing the magic address to the location corresponding to each core and then providing the IPC interrupt by using the following code.

    /* Unlock the chip registers */
    DEVICE_REG32_W(KICK0, 0x83e70b13);
    DEVICE_REG32_W(KICK1, 0x95a4f1e0);

    /* Writing the entry address to other cores */
    for (core = 1; core < pform_info.cpu.core_count; core++)
    {

    DEVICE_REG32_W(BOOT_MAGIC_ADDR(core), (uint32_t)write_boot_magic_number);

    /* Delay 1 sec */
    platform_delay(1);
    }

    /* Core0 needs to assert the IPC interrupt to the secondary cores to wake them up and so that they execute code from the location specified by the magic address*/
    for (core = 1; core < pform_info.cpu.core_count; core++)
    {
    /* IPC interrupt other cores */
    DEVICE_REG32_W(IPCGR(core), 1);
    platform_delay(1000);
    }

    Please ensure that you have the delays in place especially after the IPC interrupt to the secondary core is provided. Let us know if you were able to get this working or if you face any issues.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Prodigy 40 points

    Thank you Rahul Prabhu

    my problem has been solved already, just do that as you gave

    my prior program to generate IPC is like this:

    *((volatile u_int32 *)IPCGRx_ADDR) = 1;

    this operate maybe can not achieve the goal as next:

    /* IPC interrupt other cores */
    DEVICE_REG32_W(IPCGR(core), 1);

     

    i  didn't check the disassembly code, when I use "DEVICE_REG32_W(IPCGR(core), 1);" to generate IPC, it's OK

    many thanks