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eDMA gives up with SPI and UART simultaneously transmitting using DMA.

Mughees Chohan
Intellectual 530 points
Other Parts Discussed in Thread: OMAPL138

Hi,

I am using omapl138. We have added eDMA support in our SPI and UART drivers for our custom RTOS. I have two tasks in my environment. One task continuously transmits data via UART using eDMA and the other task transmits and receives data via SPI using DMA. The problem is that as soon as SPI starts transmitting data my UART DMA stops. The events missed register show that missed events have occurred on TX channel of UART and TX channel of SPI. SPI transfers still keep on working but UART transfers stop. I cannot figure out a reason for this. Maybe the EDMA controller cannot perform under heavy loads. Also please can someone tell me what what should one do once he get the missed event in case of UART. Thank You.

Regards,

Mughees

  • 0
    TI__Mastermind 35645 points

    Hi Mughees,

    Thanks for your post.

    I think, probably it would have lost DMA channel synchronization to UART Tx event (UTXEVT), obviously due to this, it would be disabled at the time when the UART Tx. event is generated. By this way, the DMA channel would miss the UART Tx. event and unless the UART generates a new event,  no data transfer would occur further.

    There could also one other chance for the UART activity to stop when Emulator writes and however, it would affect register contents and UART operation depending on what register is accessed and what value is writen to it.

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 530 points

    Hi Sivaraj,

    Thanks for your prompt reply. Well I do know why this is happening but I still have three questions:

    1. Why is eDMA is not capable to handle simultaneously ongoing transfers on just two peripherals?

    2. What can be done to avoid such a situation?

    3. How to recover from such a situation? Reposting my transfer on UART on missed event detection isn't a good solution. Because I may get a missed event at the middle of the transfer then I would have to know how much transfer is remaining and then repost it and its not efficient. Don't know what should I do now.

    Awaiting your reply.Thanks. 

    Best Regards,

    Mughees Ahmed Chohan

  • 0 in reply to Mughees Chohan
    Intellectual 530 points

    Ok I tried one thing. I now manually trigger a single UART event to the DMA in the EDMA_ESR register during the start of every UART DMA transfer. Now everything works fine. Seems like that the UART generates an event always whenever it finds the TX FIFO to be empty. So if the EDMA channel is not enabled the event will be missed and the UART will forever wait for data to be copied to the FIFO if in the next transfer a manual event trigger is not set. This is because in original case the data would not be copied to the UART unless UART generates an event, but the UART would have already generated an event which was missed. So the idea is to set that event manually.

  • 0 in reply to Mughees Chohan
    TI__Mastermind 35645 points

    Mughees,

    Thanks for your update.

    Good to hear this progress and I do appreciate your idea of triggering triggering UART event explicitly & now i am sure that you won't miss UART event.

    That's a great idea !

    Thanks & regards,

    Sivaraj K

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