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DM365 FBdriver supporting Digital LCD output



      I have some question about the DM365 LCD driver. To drive the LCD,mine is 480x272,Do I necessarily use logicPD encoder in the driver?(I have already connected the LCD to the digital LCD output interface)  

     I have configured the logicpd_encoder_configuration struct in file Logicpd_encoder.c,and set the boot prama davinci_enc_mngr.ch0_output=

LCD  davinci_enc_mngr.ch0_mode=480x272. and modified the logicpd_encoder_configuration in the LogicPD encoder.c to fit the LCD's timming. I think I should set the LCD's pixel clock and the pinmux to support my LCD (PRGB 888,the default seems to  be PRGB565),but if  I don't use logicPD encoder,how to set them? And If I set all of them OK,How could I know it is OK,Is there something will show in the LCD,or I have to assign the LCD something to show to prove the lcd is drived successfully? Could someone help me with these problems? Thanks
  • lots of good questions; hopefully I can add some clarity.

    Normally, you need to design your hardware with you given video requirements (such as output resolution) in mind; this way you ensure you choose the right crystal/oscillator hardware to drive your pixel clock; sure, the hardware can often multiply and divide your hardware clock, but you can only do so much with this.  Case in point, in our demos, our output video is normally 480i (when configured for composite) or 720p (when configured for component output), any other resolution you choose will be cropped, and perhaps centered within one of these two becuase the hardware pixel clock chosen on the EVM lends itself well to support these two resolutions.  In addition, these are resolutions that are well-defined (blanking area, active pixels, pixel clock requirements...) by SMPTE industry standards and hence there is concensus on how that should look; therefore my LCD display can sense the video timing signals and automatically detect I have a 720p video frame coming in despite the video data being blank, color bars, or a real picture frame.

    That said, I have not worked with 480x272 resolution enough to know if this is a defined video standard, hence it is very difficult to determine how the LCD display will behave as this depends on the resolutions the LCD display supports and its ability to automatically sense these resolutions (vs manually being set to expect a given resolution).  Most LCD displays today will sense standardized video signal such as VGA, WXGA, 480i, 720p and 1080i... Therefore the first thing I would recommend is to see if 480x272 is a widely adopted industry standard and determine if your LCD display will support it.

    From a video driver perspective, our drivers only support a limited set of video output resolutions which can be derived with the given hardware clock chosen; if you were to choose 480x272 using decode demo, this will likely be centered in a 720x480 (480i) frame and displayed.  Setting these resolutions at bootargs time may not make a difference as these bootargs configurations go straight to the driver and they will likely get rejected if that resolution is not supported (I do not think it is). 

    In addition, to implement RGB888 video output, you will need to configure a few GPIO hardware pins to extend RGB565 mode; again, this implies some driver work on your part.  These is detailed in VPBE UG: http://focus.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=sprufg9a

  • Thanks Juan.

    I have read the VPBE User Guid,And I have a little confused:

    First,I will explain  what I think:

         My lcd support 9MHz rat,So to get that ,I set the VENC_DCLKCTL=0x2, VENC_DCLKPTN0=0x1; Then I divide the ENC clock by 3,As the default  ENC clock is from PLLDIV6-SYSCLK6 which is 27 MHz; so I get the 9MHz; Corresponding,I set the VENC_OSDCLK0=0x2;VENC_OSDCLK1=0x1,that also divide the 27MHz by 3;

         If set like that,I will got a 9MHz to drive the LCD,is that enough? If not ,what else should I set? And I'm little confused about the DCKOH field in VENC_DCLKCTL, that also divide the clock , what's the difference between DCKOH and VENC_DCLKPTN dividing? also the DCKIH. And the HSPLS that used for lcd timing is counted by who,ENC clock or DCLK which have been divided?

     

  • Thanks Juan.

    I have read the VPBE User Guid,And I have a little confused:

    First,I will explain  what I think:

         My lcd support 9MHz rat,So to get that ,I set the VENC_DCLKCTL=0x2, VENC_DCLKPTN0=0x1; Then I divide the ENC clock by 3,As the default  ENC clock is from PLLDIV6-SYSCLK6 which is 27 MHz; so I get the 9MHz; Corresponding,I set the VENC_OSDCLK0=0x2;VENC_OSDCLK1=0x1,that also divide the 27MHz by 3;

         If set like that,I will got a 9MHz to drive the LCD,is that enough? If not ,what else should I set? And I'm little confused about the DCKOH field in VENC_DCLKCTL, that also divide the clock , what's the difference between DCKOH and VENC_DCLKPTN dividing? also the DCKIH. And the HSPLS that used for lcd timing is counted by who,ENC clock or DCLK which have been divided?

  • There is also another thing that I feel strange:

      I set the register  int the encoder's set mode function in the linux driver using code:

        venc_reg_out(VENC_VMOD,   0);
        venc_reg_out(VENC_LCDOUT, 1);
            venc_reg_out(VENC_HSPLS,  0x52);
            venc_reg_out(VENC_VSPLS,  0xa);
            venc_reg_out(VENC_HINT,   0x419);
            venc_reg_out(VENC_VINT,   0x11d);
            venc_reg_out(VENC_HSTART, 0x56);
            venc_reg_out(VENC_VSTART, 0xc);
            venc_reg_out(VENC_HVALID, 0x3c0);
            venc_reg_out(VENC_VVALID, 0x110);
            venc_reg_out(VENC_HSDLY,  0x0);
            venc_reg_out(VENC_VSDLY,  0x0);
            venc_reg_out(VENC_DCLKCTL,   0x802);
            venc_reg_out(VENC_DCLKPTN0,  0x100);
            venc_reg_out(VENC_DCLKPTN1,  0x0);
            venc_reg_out(VENC_DCLKPTN2,  0x0);
            venc_reg_out(VENC_DCLKPTN3,  0x0);
            venc_reg_out(VENC_OSDCLK0,   0x02);
            venc_reg_out(VENC_OSDCLK1,   0x100);
        venc_reg_out(VENC_VIDCTL, 0x2000);
        venc_reg_out(VENC_CLKCTL, 0x10);
        venc_reg_out(VENC_SYNCCTL, 0x0f);
        venc_reg_out(VENC_VMOD, 0x2011 );

    then after I boot the system,I install a module which I wrote for testing the registers.I just print the value in the registers that I set with the code above on the console,But the values are almost all stay zero,So zero may be there default values.How ever,I don't understand where they are not set as I have already set them in the code;

    Maybe I put the code in the wrong place,and they are reset by other code somewhere later. if so,where the register setting code should be placed?

    Thanks.

  • And we just connected our LCD directly to the DM365,we didn't use any interface chips.

  • Kai Luo said:

    then after I boot the system,I install a module which I wrote for testing the registers.I just print the value in the registers that I set with the code above on the console,But the values are almost all stay zero,So zero may be there default values.How ever,I don't understand where they are not set as I have already set them in the code;

    Is this a kernel module you are installing to read the register values back?  Please note that a user-level program accesses virtual memory (not physical), hence if you write a user level program to read the registers, you may not be reading the correct addresses and hence perhaps get all zeros.  After linux boots, I really doubt the registers will be all zeros (VIDCTL default is not all zeros).

  • Kai Luo said:

    And we just connected our LCD directly to the DM365,we didn't use any interface chips.

    If you are using our DM365 EVM from Spectrum Digital, then you have two analog output options (NTSC or Component); if you want to ecercise the digital LCD interface, this interface is exposed via J18, J19 and J23 daughter card connestors, which means you will need (probrably design your own) daughter card to sit on top of these connectors.  Is this what you are doing?  Please see the EVM Tech Ref manual available at http://support.spectrumdigital.com/boards/evmdm365/revc/

     

     

  • Juan Gonzales said:

    And we just connected our LCD directly to the DM365,we didn't use any interface chips.

    If you are using our DM365 EVM from Spectrum Digital, then you have two analog output options (NTSC or Component); if you want to ecercise the digital LCD interface, this interface is exposed via J18, J19 and J23 daughter card connestors, which means you will need (probrably design your own) daughter card to sit on top of these connectors.  Is this what you are doing?  Please see the EVM Tech Ref manual available at http://support.spectrumdigital.com/boards/evmdm365/revc/

     

     

    [/quote]

    Yes,we connect the LCD through J18 J19 J23 ,we use a card to connect the LCD's pin to J18 J19 J23.Is that means I will need to use the logicPD encoder in the driver?

    Also ,is the register setting  VENC_DCLKCTL=0x2, VENC_DCLKPTN0=0x1 can divide the clock by 3? And the HSPLS that used for lcd timing is counted by who,ENC clock or DCLK which have been divided?

  • It seems  VENC_DCLKCTL=0x2, VENC_DCLKPTN0=0x1 can divide the clock by 3

  • The module is installed by

    zero said:

    It seems  VENC_DCLKCTL=0x2, VENC_DCLKPTN0=0x1 can divide the clock by 3

    The module is installed by insmod command. So the module should be running in the kernal space and can read the regisers.

    It's my mistake that the registers are not all zero,but many of them are.I didn't test all of them,just the registers I just modifyed. The VIDCTL and VMOD are of the proper value. But many others like HSPLS,VSPLS,VINT,HSDLY,DCLKCTL,OSDCLK0 ,which I modifyed,are zero.Why is that?

  • Juan Gonzales said:

    Is this a kernel module you are installing to read the register values back?  Please note that a user-level program accesses virtual memory (not physical), hence if you write a user level program to read the registers, you may not be reading the correct addresses and hence perhaps get all zeros.  After linux boots, I really doubt the registers will be all zeros (VIDCTL default is not all zeros).

    Yes,it's a kernel module,so it should be running in the kernel space.

    The registers are not all zero,but many of them are.I didn't test all of them,just the registers I just modifyed. The VIDCTL and VMOD are of the proper value. But many others like HSPLS,VSPLS,VINT,HSDLY,DCLKCTL,OSDCLK0 ,which I modifyed,are zero.Why is that?

  • Hi Juan:

    Can I get a proper 9MHz with HSPLS and VSPLS work well , if I set the register like this:

           venc_reg_out(VENC_DCLKCTL,   0x802);

            venc_reg_out(VENC_DCLKPTN0,  0x100);
            venc_reg_out(VENC_DCLKPTN1,  0x0);
            venc_reg_out(VENC_DCLKPTN2,  0x0);
            venc_reg_out(VENC_DCLKPTN3,  0x0);
            venc_reg_out(VENC_OSDCLK0,   0x02);
            venc_reg_out(VENC_OSDCLK1,   0x100);

    And if I connect the LCD to the DM365 EVM via J18 J19 J23,to drive the LCD ,should I use the logicPD encoder and fix it to fit our LCD's timing  in the linux driver?

  • I have modified the logicpd_encoder.c and set the proper boot arguments.After the system boot up,when I input the command cat /sys/class/davinci_display/ch0/output and cat /sys/class/davinci_display/ch0/mode.It returns LCD and 480x272.so the logicpd_encoder and encoder_manager works well.But I still can't see any output on the LCD.I don't know why. And I'm not sure whether the registers I set really can got a 9HMz or not. I will appreciate any help!

     

  •  By setting :
       venc_reg_out(VENC_DCLKCTL,   0x802);
       venc_reg_out(VENC_DCLKPTN0,  0x4);
       venc_reg_out(VENC_DCLKPTN1,  0x0);
       venc_reg_out(VENC_DCLKPTN2,  0x0);
       venc_reg_out(VENC_DCLKPTN3,  0x0);
       venc_reg_out(VENC_OSDCLK0,   0x2);
       venc_reg_out(VENC_OSDCLK1,   0x4);
    We have hooked an oscilloscope to the VCLK line and we could see the 9MHz output which we want now.But There is a problem that I can't understand.
    According to our LCD's timing,if I set the pixclock 9MHz , the Hsync cycle should be about 17.14KHz and Vsync cycle should be about 59.94Hz,but the oscilloscope shows that they are 55KHz and 200Hz. And then I set the register again and make the VCLK line 6.7MHz,But  the Hsync and Vsync cycle still kept 55KHz and 200Hz. I can't understand.Isn't the Hsync and Vsync single based on the VCTL(pixclock)?

     

  • Plase note that VPBE User Guide suggests that HYSNC and VSYNC are driven by the encoder clock; the settings above may change DCLK which can be output via VCLK pin, but this does not change ENC clock and consequently HSYNC and VSYNC.  If you are doing a simple divide by 2, 4, or some multiple... you may be able to program your HINT, VINT and similar registers differently to account for the fact that you are changing the pixel clock.

  • hi, L,

    do you get any updates here ?

    we are trying with the same architecture as yours but ... we are trying with our custom boards.

    i just change the command line to

    bootargs console=ttyS0,115200n8 rw mem=54M 
    video=davincifb:vid0=OFF:vid1=OFF:osd0=640x480x16,4050K 
    dm365_imp.oper_mode=0 
    davinci_enc_mngr.ch0_output=LCD 
    davinci_enc_mngr.ch0_mode=640x480 
    root=/dev/nfs nfsroot=10.22.5.222:/opt/ti/targetfs 
    ip=10.22.5.223

    and now our LCD get blank with white.. still i dont konw where should i get start to modify it .

    i found that the  code of venc_reg_out but i dont konown how to get the vaule .

    we are using dvsdk4.0 and rgb888 is better.

    regrads, Mike.