We are having a problem with our Keystone II EVMK2H and XTCIEVMK2X boards getting the SRIO_TputBenchmarkingK2HC66TestProject project working through a NAT-MCH SRIO switch. The default internal loopback version of this program works fine but when setup to use an external switch it hangs in SRIO Lane Configuration. We running using CCS over JTAG and the XDS200 onboard emulator. The backplanes routes ports 8 thru 11 to the MCH SRIO switch Fabric D-G ports. Everything looks good there. In benchmark.h we change “IS_BOARD_TO_BOARD” to TRUE and “IS_OVER_ EXTERNAL_SRIO_SWITCH” to TRUE. When we run the program it hangs in one of two places:
1) In srio_laneconfig.c
//SB PLL Status Poll
do
{
pllstat = CSL_SrioSerdesGetStatus(CSL_SRIO_SERDES_CFG_REGS, 4);
}while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);
Note: pllstat is continuously 0
OR
2) We have seen it get by there and then again In srio_laneconfig.c it fails the 5-10 second loop:
while (CSL_tscRead() < tscTemp)
{
if (CSL_SRIO_IsPortOk (hSrio, port) == TRUE)
{
sprintf (statusText,"");
break;
}
}
and says: "Debug: SRIO port 0 is NOT operational"
We are using the default four x1 lanes of 5Gbps (each lane). We have to manually enable the SRIO Switch port connected to the AMC slot (set for a 4 x1 5G/s lanes) becuase the Keystone II boards to not have the MMC code implemented so uTCA E-Keying does not work.
Can someone help us understand why the PLL is not getting locked ot why it is failing at thes points? Is it because it it not seeing the proper SERDES signal from the switch? The switch is not seeing a link either.
We are running the CONSUMER on Core 0 of the first board but never get to start the PRODUCER on Core 1 of the other board because we cant get by this point.
Todd