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AM335x GPMC behavior issue

WTMEC_Will Hsu
Expert 2620 points

Hi TI team,
I used a GPMC example on beagle bone. (http://e2e.ti.com/support/arm/sitara_arm/f/791/p/176492/644595.aspx#644595)
I set GPMC for 16-Bit Address/Data-Multiplexed as Figure 7-3.

My test results as follows

GPMC output:

When i write low-byte data (D0-D7), BE0n will be low-level and BE1n will be high-level.

When i write high-byte data (D8-D15), BE0n will be high-level and BE1n will be low-level.

GPMC input:

When I read low-byte data (D0-D7), BE0n and BE1n will be low-level.

When I read high-byte data (D8-D15), BE0n and BE1n will be low-level.

 

The problem is that when I read low-byte data or high-byte data,  BE0n and BE1n will be low-level.

Why BE0n and BE1n will be low-level at the same time???

Please help~~

Thanks

From Will Hsu

  • 0
    TI__Guru**** 393215 points

    Hi Will,

    I will ask the factory team to look at this.

  • 0
    TI__Genius 9190 points

    Hello Will, 

    the BE pins are output only so if you are doing a read they will not toggle.  If you have the GPMC setup in 16b mode and connected to a 16b memory then when you read it should be giving all 16b during the read.  for the write, you must be doing an 8b write to the memory which would explain why the BE pins are toggling.  

  • 0 in reply to Jeff Culverhouse
    Mastermind 8040 points

    Jeff Culverhouse said:

    the BE pins are output only so if you are doing a read they will not toggle

    Assuming that by "output only" you meant "used for writes only" (obviously they are always outputs)... while this would make some sense, since for memories it wouldn't matter (although the same is of course not necessarily true for memory-mapped devices), the TRM says otherwise:

    7.1.3.3.8.3.12 Byte Enable (BE1n/BE0n)

    Byte enable signals (BE1n/BE0n) are:

      • Valid (asserted or nonasserted according to the incoming system request) from access start to access completion for asynchronous and synchronous single accesses
      • Asserted low from access start to access completion for asynchronous and synchronous multiple read accesses
      • Valid (asserted or nonasserted, according to the incoming system request) synchronously to each written data for synchronous multiple write accesses

    And the timing diagrams for single reads also show nBE toggling (as opposed to those for burst reads which show nBE held low)

  • 0
    Genius 3685 points

    I assume that the GPMC is doing a 16bit read, and the unused byte is not used.

    The exact behaviour of the GPMC for doing 8bit reads to 16bit memories is not explained in the data sheet.

    Are both OEN signals valid ?


    regards

    Wolfgang