DDR2 not operation on custom AM3352 board

More info.

All of the DDR2 pins appear to be doing it's thing.

I see refresh commands, Write and Read requests, banks toggling.

However, it appears that DDR2 does not respond to read request:

DQS signals are not toggling and the data is not output following ACTIVATE and READ commands by the DDR controller on AM3352.

Did you change the pagesize to 3 (10 column bits)?

UPDATE: As nchukeg points out later that should be 2.  Sorry!

Oleg, according to the datasheet for that part, the CL=5 which means the READ_LATENCY is 6.  I think if you change these 2 parameters in the EMIF configuration, that should resolve your read issues.

Regards,

James

The pages size was set to 3,  CL set to 5 and Read latency set to 6. Still no luck. Is there any clues to the fact that the memory only ever reads zero? I would suspect even if the timing was off that we would see garbage in the memory?

What software is being used to configure the EMIF?  Is this your own software, or is it something like u-boot or even a gel file?

Can you please try running this diagnostic script I wrote:

http://git.ti.com/am335x-dss-scripts/am335x-dss-scripts/blobs/master/am335x-ddr-analysis.dss

The usage instructions are basically the same as this other script:

http://processors.wiki.ti.com/index.php/AM335x_Clock_Tree_Tool#Importing_Data_from_Actual_Hardware

Please attach the generated file to the thread.  Admittedly I wrote the file with DDR3 as the primary target, though it should still give us some insights into DDR2.  This might be a good opportunity for me to improve the script depending on what we find...

Tried with both a gel file (jlink) and uboot spl.  I will try the script out.

Hi Russ, let's back up a bit and confirm a few things:

-what frequency are you running the DDR?  I assume 266MHz?

-I think the SDRAM_CONFIG register should be  0x4180_5632.  The only things that changed from the EVM are row size (13 bits) and CL=5.

-READ_LATENCY=6 as we have said already

-did you got through the timing spreadsheet as well? I agree that this probably isn't causing all zeros, but this needs to be filled out correctly to ensure proper operation

http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips#AC_timing_registers

-I haven't checked your PHY regs, but if you used the spreadsheet, you should be OK.

Try these out and keep me up to date.  If you are still stuck, we can try to arrange a call.

Regards,

James

I tried to run the script, but I get an error (see picture).

Yes 266.

I tried 0x4180_5632 with read_latency 6 with the same result.

We did work through the spread sheet (from post above)

3) DDR2 PHY registers were configured according to the excel spreadsheet on http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips#Setting_Refresh_rate

with DDR_CK trace set to 1.312 and 1.312 for both bytes

      DDR_DQSx set to 1.1162 for byte 0 and 1.137 for byte 1

     PHY_INVERT_CLKOUT is set to 0

This resulted in

#define MT47H64M16HR25EITH_RD_DQS             0x40

#define MT47H64M16HR25EITH_PHY_FIFO_WE   0x6B

#define MT47H64M16HR25EITH_WR_DQS             0x2

#define MT47H64M16HR25EITH_PHY_WR_DATA   0x40

#define MT47H64M16HR25EITH_RATIO                  0x80

Ok I got the script to run here are the results

EMIF: SDRAM_CONFIG = 0x41805632
* Bits 26:24 (reg_ddr_term) set for 75 Ohm (001b)
* Bits 19:18 (reg_sdram_drive) set for normal drive (00b)
EMIF: PWR_MGMT_CTRL = 0x00000000
DDR PHY: DDR_PHY_CTRL_1 = 0x00000006
* Bits 9:8 (reg_phy_rd_local_odt) configured as no termination (00b)
CONTROL: DDR_CMD0_IOCTRL = 0x0000018b
* Bits 9:5 control ddr_ck and ddr_ckn
- Slew slow
- Drive Strength 9 mA
* Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
- Slew slow
- Drive Strength 8 mA
CONTROL: DDR_CMD1_IOCTRL = 0x0000018b
* Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
- Slew slow
- Drive Strength 8 mA
CONTROL: DDR_CMD2_IOCTRL = 0x0000018b
* Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
- Slew slow
- Drive Strength 8 mA
CONTROL: DDR_DATA0_IOCTRL = 0x0000018b
* Bits 9:5 control ddr_dqs1, ddr_dqsn1
- Slew slow
- Drive Strength 9 mA
* Bits 4:0 control ddr_d[15:8], ddr_dqm1
- Slew slow
- Drive Strength 8 mA
CONTROL: DDR_DATA1_IOCTRL = 0x0000018b
* Bits 9:5 control ddr_dqs0, ddr_dqsn0
- Slew slow
- Drive Strength 9 mA
* Bits 4:0 control ddr_d[7:0], dqm0
- Slew slow
- Drive Strength 8 mA
CONTROL: DDR_IO_CTRL = 0x00000000
* Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00010167
CONTROL: VREF_CTRL = 0x00000000
CONTROL: DDR_CKE_CTRL = 0x00000001

nchukeg said:

DQS signals are not toggling and the data is not output following ACTIVATE and READ commands by the DDR controller on AM3352.

The fact that you don't see DQS toggling AT ALL seems like something is drastically wrong, i.e. not just a minor timing issue or something along those lines.  I would suggest:

1. Double-check your pin-out of the DDR2 device, i.e. make sure there's no error in transcribing from data manual to symbol.
2. Measure impedance from DDR2's power to ground.
3. Triple check that the proper voltages are seen on the DDR2.

Hello,

Few things

1) I think page size must be 2

page 595 of the RFM:

Page Size.
Defines the internal page size of connected SDRAM devices.
Set to 0 for
256-word page (8 column bits), set to 1 for
512-word page (9 column bits), set to 2 for
1024-word page (10 column bits), and set to 3 for
2048-word page (11 column bits).
All other values are reserved.

2) I think CL should be 4.  That's what it was for the EVM kit as well.

On page 2 of the SDRAM sheet our speed speed grade is -25E and the data rate is 533 (266 x 2) which gives CL of 4

3) The software is the slightly altered version of spl provided by TI for AM335X evm where the difference so far are

DDR settings as described above

PIN mux configuration

We do not read EEPROM on EVM to figure out what type of the board we are and just assume the type.

4) When I break after configuring the DDR2 and attempt to write to memory address.  On the scope I see a write command followed by a read command.

The read command where DDR2 is in control of DQS and Data they are both low which tells me that DDR2 is simply not responding.  Since all of the lines are low, all zeros are interpreted by memory viewer

Russ Fritch said:

Ok I got the script to run here are the results

What was needed to get the script to run?  I don't see anything obviously wrong there.

nchukeg said:

1) I think page size must be 2

page 595 of the RFM:

Page Size.
Defines the internal page size of connected SDRAM devices.
Set to 0 for
256-word page (8 column bits), set to 1 for
512-word page (9 column bits), set to 2 for
1024-word page (10 column bits), and set to 3 for
2048-word page (11 column bits).
All other values are reserved.

Correct.  Sorry for my earlier mistake.  I made a note in my previous post to avoid creating confusion for anyone else.  Thanks for pointing that out!

nchukeg said:

2) I think CL should be 4.  That's what it was for the EVM kit as well.

On page 2 of the SDRAM sheet our speed speed grade is -25E and the data rate is 533 (266 x 2) which gives CL of 4

I just went and downloaded the data sheet for the MT47H64M16 and page 2 shows CL=5.

nchukeg said:

3) The software is the slightly altered version of spl provided by TI for AM335X evm where the difference so far are

DDR settings as described above

PIN mux configuration

We do not read EEPROM on EVM to figure out what type of the board we are and just assume the type.

Sounds fine.

nchukeg said:

4) When I break after configuring the DDR2 and attempt to write to memory address.  On the scope I see a write command followed by a read command.

The read command where DDR2 is in control of DQS and Data they are both low which tells me that DDR2 is simply not responding.  Since all of the lines are low, all zeros are interpreted by memory viewer

Still seems like something much bigger is going on here, i.e. not just timing related.  Power is my usual suspect for these situations...

Maybe it was documented somewhere, but I missed it.  I just needed to modify the openSession to point to my debug configuration. 

debugSessionDAP = ds.openSession("*", "CortxA8");//"CS_DAP_DebugSS");

1) OK

2) VDDQ is 3.8 KOhm, Vref is 2.6 KOhm

3) VDDQ is 1.8 and Vref is .9 as specified in the data sheet

For clarification we are using a single  MT47H64M16HR-25EITH  where the EVM was using two MT47H256M8 .

I havent read anything in th am335x datasheet that specifies  what needs to change in the cpu to know if there are two chips or one.  Can anyone give any insight into this?

Russ Fritch said:

I havent read anything in th am335x datasheet that specifies  what needs to change in the cpu to know if there are two chips or one.  Can anyone give any insight into this?

Correct -- there's no specific setting for that.  It's comprehended in the row and column address bits.

Hi Russ, just a few other things which may not be related, but would need to get fixed anyway.

I went through the DDR2 datasheet and with the spreadsheet and came up with the following AC timing register values which you should be using:

SDRAM_TIM_1 = 0x0666A391

SDRAM_TIM_2 = 0x242431CA

SDRAM_TIM_3 = 0x0000021F

Also, i show the refresh rate in the DDR2 data sheet as 3.9607us for an automotive part, which would correspond to DDR2_REF_CTRL = 0x41D  (1053 decimal)

-Are you seeing the same thing across multiple boards?

Regards,

James

We are seeing it across multiple boards. I updated to the latest timings . Sill all 0's. Thanks for the help thus far.

Im trashing now....  but if it I  set CL to 2 I the memory window changes from all zeroes to 00ff00ff  0000000 .....