Other Parts Discussed in Thread: 66AK2E05
I'm trying to bring up the PCIe 1 connection with the PCIe-to-SATA chip 88SE9182A2 on K2E EVM(https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html).
But the LTSSM alway stays between 0x02(POLL_ACTIV) and 0x06(DETECT_WAIT). I've made the SerDes configuration same as MCSDK(veriosn is 3_01_00_03) . I also connect the SATA port with an SSD with power supply.
I run the PDK example project PCIE_K2EC66BiosExampleProject with below changes, the result is same.
/**changes to pdk_keystone2_3_01_00_03/packages/ti/drv/pcie/example/sample/src/pci_sample.c**/
Add following code fragment to pciePowerCfg() before 'return pcie_RET_OK;':
#if defined(DEVICE_K2E)
if (CSL_PSC_getPowerDomainState (18) != PSC_PDSTATE_ON) {
/* Enable the domain */
CSL_PSC_enablePowerDomain (18);
/* Enable MDCTL */
CSL_PSC_setModuleNextState (27, PSC_MODSTATE_ENABLE);
/* Apply the domain */
CSL_PSC_startStateTransition (18);
/* Wait for it to finish */
while (! CSL_PSC_isStateTransitionDone (18));
} else {
System_printf ("Power domain is already enabled. You probably re-ran without device reset (which is OK)\n");
}
#endif
Change in main():
if ((retVal = Pcie_open(0, &handle)) != pcie_RET_OK)
to
if ((retVal = Pcie_open(1, &handle)) != pcie_RET_OK)
/** end of change to pdk_keystone2_3_01_00_03/packages/ti/drv/pcie/example/sample/src/pci_sample.c**/
I also see Bit[4:3] of DEVCFG are reserved in SPRS865B(66AK2E05/2) document, but it is used to determine the working mode of PCIe 1 according to the PDK example code. Does the document need to be updated?
