Warm reset problem for AM3517 with TPS65910 during I2C interface

Hi Kazu-san,

Warm reset is a global device reset that affects almost the entire processor. There is no way I2C to continue functioning once it's asserted. Maybe a possible solution to your problem could be to have I2C pins double-connected to a couple of GPIOs that will give you the ability to monitor SDA after reset and if necessary inject SCL clocks to bring the bus out of hanging state.

Hello Biser,

Thank you for your advice. Do you mean the connection below?

1) Connect SDA pin of PMIC to i2c1_sda and gpio_xx of AM3517.

2) Connect SCL pin of PMIC to i2c1_scl and gpio_yy of AM3517.

gpio_yy sends some pulses if gpio_xx is low level. Is it correct?

Regards,
Kazu

Yes, something like that. Of course care must be taken about pinmuxing the GPIOs correctly, so as not to interfere with I2C, and also choose GPIOs that will not block I2C in their default reset release state.

Hello Biser,

Thank you for your quick reply. If possible, I don't want to modify PCB. If AM3517 UART reads data from slave address zero configured I2C_SA register, I think the pulse is similar to "free data format". Actually there is not a device as slave address zero. But I'm anxious about signal collision with PMIC on SDA line. What do you think?

Regards,
Kazu

I'm afraid I don't understand.

I'm not a SW expert, but should be something like that.

Hello Biser,

I appreciate your support. I can send 9 clock pulses on SCL using SCL_O bit of I2C_SYSTEST resister on logicPD AM3517EVM. I also configure this register in order to enter test mode before sending pulses. First I set ST_EN, then set SCL_O and SDA_O, finally I set TMODE as "loop back + SDA/SCL IO mode select". I’m worried about a behavior after this process. I seem that SCL and SDA falls for only a moment after I set TMODE. I see that they are high level before this process, and I set them as high level. Do you know why they fall once? I think their level should be kept high level to begin recovery operation of slave.

Regards,
Kazu

Can you try another sequence instead:

ST_EN=1

TMODE=2

Poll SDA_I until it becomes 1

TMODE=0

ST_EN=0

Hello Biser,

Thank you for your advice. I don't need to set SCL_O and SDA_O, do I? But SCL falls to a low level before polling SDA level if I don't set SCL_O. Because the initial value of SCL_O is zero(a low level). I don't want to send SCL as a low level when SDA level is high which means PMIC is not hang-up. Do you have any suggestion?

Regards,
Kazu

Well, then perhaps the very first step should be to check SDA_I and if it's high just skip the whole procedure.

Hello Biser,

I configure and read registers to check SDA level.

ST_EN=1

TMODE=2

-> Regardless of SDA level, SCL is falling at this timing.

Poll SDA_I until it becomes 1

Regards,
Kazu

What I mean is that you try to check if SDA_I=1 before ST_EN=1.

Hello Biser,

SDA signal doesn't propagate internally from SDA pin to SDA_I bit without setting TMODE to SDA/SCL I/O mode. And also, TMODE isn't enabled without setting ST_EN. The result is the same even if I set ST_EN, TMODE, SDA_O and SCL_O at a time. The level of SDA and SCL is low for 200 nano second. The level ramps up slowly, then comes up to high after 1 micro second. Could you give me some advice?

Regards,
Kazu

I see. I was hoping that SDA_I can be read without switching to test mode, but it seems this is not possible. I don't see anything that can be done to avoid this drop on I2C lines when switching to test mode.

Hello Biser,

I see, thank you anyway. I think the drop is not caused a condition of start bit, so I hope PMIC will ignore the drop. I think this check method is applicable to release PMIC, so we're going to test on the target board. I appreciate your help.

Regards,
Kazu